armv7m: Honour CCR.USERSETMPEND
The CCR.USERSETMPEND bit has to be set to permit unprivileged code to write to the Software Triggered Interrupt register; honour this bit rather than letting any code write to the register. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1485285380-10565-9-git-send-email-peter.maydell@linaro.org [PMM: Tweak commit message, comment, phrasing of condition] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -409,7 +409,10 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
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"NVIC: Aux fault status registers unimplemented\n");
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break;
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case 0xf00: /* Software Triggered Interrupt Register */
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if ((value & 0x1ff) < s->num_irq) {
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/* user mode can only write to STIR if CCR.USERSETMPEND permits it */
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if ((value & 0x1ff) < s->num_irq &&
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(arm_current_el(&cpu->env) ||
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(cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {
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gic_set_pending_private(&s->gic, 0, value & 0x1ff);
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}
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break;
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