macio: switch over to new byte-aligned DMA helpers
Now that the DMA helpers are byte-aligned they can be called directly from the macio routines rather than emulating byte-aligned accesses via multiple block-level accesses. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Message-Id: 1476445266-27503-3-git-send-email-mark.cave-ayland@ilande.co.uk Signed-off-by: John Snow <jsnow@redhat.com>
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99868af3d0
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213
hw/ide/macio.c
213
hw/ide/macio.c
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@ -52,187 +52,6 @@ static const int debug_macio = 0;
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#define MACIO_PAGE_SIZE 4096
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/*
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* Unaligned DMA read/write access functions required for OS X/Darwin which
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* don't perform DMA transactions on sector boundaries. These functions are
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* modelled on bdrv_co_preadv()/bdrv_co_pwritev() and so should be easy to
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* remove if the unaligned block APIs are ever exposed.
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*/
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static void pmac_dma_read(BlockBackend *blk,
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int64_t offset, unsigned int bytes,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr;
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int64_t sector_num;
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int nsector;
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uint64_t align = BDRV_SECTOR_SIZE;
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size_t head_bytes, tail_bytes;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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sector_num = (offset >> 9);
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nsector = (io->len >> 9);
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MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
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"sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
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sector_num, nsector);
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dma_addr = io->addr;
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io->dir = DMA_DIRECTION_FROM_DEVICE;
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io->dma_len = io->len;
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io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len,
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io->dir);
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if (offset & (align - 1)) {
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head_bytes = offset & (align - 1);
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MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
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"discarding %zu bytes\n", sector_num, head_bytes);
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qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
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bytes += offset & (align - 1);
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offset = offset & ~(align - 1);
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}
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qemu_iovec_add(&io->iov, io->dma_mem, io->len);
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if ((offset + bytes) & (align - 1)) {
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tail_bytes = (offset + bytes) & (align - 1);
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MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
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"discarding bytes %zu\n", sector_num, tail_bytes);
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qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
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bytes = ROUND_UP(bytes, align);
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}
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
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"nsector: %x\n", (offset >> 9), (bytes >> 9));
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s->bus->dma->aiocb = blk_aio_preadv(blk, offset, &io->iov, 0, cb, io);
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}
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static void pmac_dma_write(BlockBackend *blk,
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int64_t offset, int bytes,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr;
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int64_t sector_num;
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int nsector;
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uint64_t align = BDRV_SECTOR_SIZE;
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size_t head_bytes, tail_bytes;
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bool unaligned_head = false, unaligned_tail = false;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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sector_num = (offset >> 9);
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nsector = (io->len >> 9);
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MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
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"sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
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sector_num, nsector);
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dma_addr = io->addr;
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io->dir = DMA_DIRECTION_TO_DEVICE;
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io->dma_len = io->len;
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io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len,
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io->dir);
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if (offset & (align - 1)) {
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head_bytes = offset & (align - 1);
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sector_num = ((offset & ~(align - 1)) >> 9);
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MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
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PRId64 "\n", sector_num);
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blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
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qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
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qemu_iovec_add(&io->iov, io->dma_mem, io->len);
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bytes += offset & (align - 1);
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offset = offset & ~(align - 1);
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unaligned_head = true;
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}
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if ((offset + bytes) & (align - 1)) {
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tail_bytes = (offset + bytes) & (align - 1);
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sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
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MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
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PRId64 "\n", sector_num);
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blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
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if (!unaligned_head) {
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qemu_iovec_add(&io->iov, io->dma_mem, io->len);
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}
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qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
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align - tail_bytes);
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bytes = ROUND_UP(bytes, align);
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unaligned_tail = true;
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}
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if (!unaligned_head && !unaligned_tail) {
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qemu_iovec_add(&io->iov, io->dma_mem, io->len);
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}
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
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"nsector: %x\n", (offset >> 9), (bytes >> 9));
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s->bus->dma->aiocb = blk_aio_pwritev(blk, offset, &io->iov, 0, cb, io);
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}
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static void pmac_dma_trim(BlockBackend *blk,
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int64_t offset, int bytes,
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void (*cb)(void *opaque, int ret), void *opaque)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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dma_addr_t dma_addr;
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qemu_iovec_destroy(&io->iov);
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qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
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dma_addr = io->addr;
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io->dir = DMA_DIRECTION_TO_DEVICE;
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io->dma_len = io->len;
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io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len,
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io->dir);
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qemu_iovec_add(&io->iov, io->dma_mem, io->len);
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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s->bus->dma->aiocb = ide_issue_trim(offset, &io->iov, cb, io, blk);
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}
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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@ -244,6 +63,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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if (ret < 0) {
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MACIO_DPRINTF("DMA error: %d\n", ret);
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qemu_sglist_destroy(&s->sg);
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ide_atapi_io_error(s, ret);
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goto done;
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}
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@ -258,6 +78,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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if (s->io_buffer_size <= 0) {
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MACIO_DPRINTF("End of IDE transfer\n");
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qemu_sglist_destroy(&s->sg);
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ide_atapi_cmd_ok(s);
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m->dma_active = false;
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goto done;
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@ -282,7 +103,15 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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/* Calculate current offset */
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offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
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pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
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qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
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&address_space_memory);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
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pmac_ide_atapi_transfer_cb, io);
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return;
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done:
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@ -310,6 +139,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
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if (ret < 0) {
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MACIO_DPRINTF("DMA error: %d\n", ret);
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qemu_sglist_destroy(&s->sg);
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ide_dma_error(s);
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goto done;
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}
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@ -324,6 +154,7 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
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if (s->io_buffer_size <= 0) {
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MACIO_DPRINTF("End of IDE transfer\n");
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qemu_sglist_destroy(&s->sg);
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s->bus);
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m->dma_active = false;
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@ -338,15 +169,27 @@ static void pmac_ide_transfer_cb(void *opaque, int ret)
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/* Calculate number of sectors */
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offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
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qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
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&address_space_memory);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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s->io_buffer_size -= io->len;
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s->io_buffer_index += io->len;
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io->len = 0;
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
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s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
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pmac_ide_atapi_transfer_cb, io);
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break;
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case IDE_DMA_WRITE:
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pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
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s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
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pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_TRIM:
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pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
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s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
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offset, 0x1, ide_issue_trim, s->blk,
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pmac_ide_transfer_cb, io,
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DMA_DIRECTION_TO_DEVICE);
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break;
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default:
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abort();
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