target/arm: Add new-in-v8M SFSR and SFAR
Add the new M profile Secure Fault Status Register and Secure Fault Address Register. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-10-git-send-email-peter.maydell@linaro.org
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@ -1017,6 +1017,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
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goto bad_offset;
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}
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return cpu->env.pmsav8.mair1[attrs.secure];
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case 0xde4: /* SFSR */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
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goto bad_offset;
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}
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if (!attrs.secure) {
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return 0;
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}
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return cpu->env.v7m.sfsr;
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case 0xde8: /* SFAR */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
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goto bad_offset;
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}
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if (!attrs.secure) {
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return 0;
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}
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return cpu->env.v7m.sfar;
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default:
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
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@ -1368,6 +1384,24 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
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* only affect cacheability, and we don't implement caching.
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*/
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break;
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case 0xde4: /* SFSR */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
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goto bad_offset;
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}
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if (!attrs.secure) {
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return;
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}
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cpu->env.v7m.sfsr &= ~value; /* W1C */
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break;
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case 0xde8: /* SFAR */
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if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
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goto bad_offset;
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}
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if (!attrs.secure) {
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return;
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}
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cpu->env.v7m.sfsr = value;
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break;
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case 0xf00: /* Software Triggered Interrupt Register */
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{
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int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;
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@ -443,8 +443,10 @@ typedef struct CPUARMState {
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uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
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uint32_t hfsr; /* HardFault Status */
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uint32_t dfsr; /* Debug Fault Status Register */
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uint32_t sfsr; /* Secure Fault Status Register */
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uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
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uint32_t bfar; /* BusFault Address */
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uint32_t sfar; /* Secure Fault Address Register */
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unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
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int exception;
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uint32_t primask[M_REG_NUM_BANKS];
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@ -1260,6 +1262,16 @@ FIELD(V7M_DFSR, DWTTRAP, 2, 1)
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FIELD(V7M_DFSR, VCATCH, 3, 1)
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FIELD(V7M_DFSR, EXTERNAL, 4, 1)
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/* V7M SFSR bits */
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FIELD(V7M_SFSR, INVEP, 0, 1)
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FIELD(V7M_SFSR, INVIS, 1, 1)
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FIELD(V7M_SFSR, INVER, 2, 1)
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FIELD(V7M_SFSR, AUVIOL, 3, 1)
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FIELD(V7M_SFSR, INVTRAN, 4, 1)
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FIELD(V7M_SFSR, LSPERR, 5, 1)
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FIELD(V7M_SFSR, SFARVALID, 6, 1)
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FIELD(V7M_SFSR, LSERR, 7, 1)
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/* v7M MPU_CTRL bits */
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FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
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FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
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@ -276,6 +276,8 @@ static const VMStateDescription vmstate_m_security = {
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VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),
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VMSTATE_UINT32(env.v7m.sfsr, ARMCPU),
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VMSTATE_UINT32(env.v7m.sfar, ARMCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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