MIPS patches 2015-02-13
Changes: * bug fixes, cleanups and minor improvements -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJU339xAAoJEFIRjjwLKdpr3P8H/38mzAuCwu+T/kz6oqEq/Vcb Bdr+BZh8p9SUjBVbjiOvhVlaL0tvm5FaVyZ/QGe6aEFuxsNjCFgQUZfj52sxRM1y +qBCrpbgyRrpGMGvIJ10ApciqWcxrGAlSpQiJv8U7fFOKBmwo6qXR4uXdWKEZWmG ltDpESqQT6FQpwE2QhncNNcShrMoPts5S8anaPDaC2AtqGe2qQwHNH4pzVkbWUXY VRFuS7BPhkMeks9HbkMIrFDwYw1i9Uq6s7B5ETzhig2lhYJ5yh3E6rm2szDEyqnn hWT79+YmA7FVNIbuzP8QF49aM4QmjdULXogK8cjdq0497O/4fgP4uJv7pttoikU= =UahQ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/lalrae/tags/mips-20150213-2' into staging MIPS patches 2015-02-13 Changes: * bug fixes, cleanups and minor improvements # gpg: Signature made Sat Feb 14 17:01:37 2015 GMT using RSA key ID 0B29DA6B # gpg: Can't check signature: public key not found * remotes/lalrae/tags/mips-20150213-2: linux-user: correct stat structure in MIPS N32 target-mips: pass 0 instead of -1 as rs in microMIPS LUI instruction target-mips: fix broken snapshotting target-mips: use CP0EnLo_XI instead of magic number target-mips: ll and lld cause AdEL exception for unaligned address target-mips: fix detection of the end of the page during translation target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processors isa: remove isa_mem_base variable gt64xxx: remove isa_mem_base usage piix4: use PCI address space instead of system memory mips: remove isa_mem_base usage jazz: remove usage of isa_mem_base jazz: do not explode QEMUMachineInitArgs structure isa: add memory space parameter to isa_bus_new Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
bf2fd13af3
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@ -920,7 +920,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
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{
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qemu_irq isa_pci_irq, *isa_irqs;
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*isa_bus = isa_bus_new(NULL, &s->pchip.reg_io);
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*isa_bus = isa_bus_new(NULL, get_system_memory(), &s->pchip.reg_io);
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isa_pci_irq = *qemu_allocate_irqs(typhoon_set_isa_irq, s, 1);
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isa_irqs = i8259_init(*isa_bus, isa_pci_irq);
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isa_bus_irqs(*isa_bus, isa_irqs);
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@ -2907,7 +2907,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object *owner,
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bank, 1);
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}
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memory_region_add_subregion_overlap(system_memory,
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isa_mem_base + 0x000a0000,
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0x000a0000,
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&s->low_mem_container,
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1);
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memory_region_set_coalescing(&s->low_mem);
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@ -64,7 +64,7 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp)
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isa_register_portio_list(isadev, 0x1ce, vbe_ports, s, "vbe");
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}
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memory_region_add_subregion_overlap(isa_address_space(isadev),
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isa_mem_base + 0x000a0000,
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0x000a0000,
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vga_io_memory, 1);
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memory_region_set_coalescing(vga_io_memory);
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s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
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@ -177,7 +177,6 @@ static void vga_update_memory_access(VGACommonState *s)
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size = 0x8000;
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break;
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}
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base += isa_mem_base;
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memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
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"vga.chain4", &s->vram, offset, size);
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memory_region_add_subregion_overlap(s->legacy_address_space, base,
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@ -2218,7 +2217,7 @@ void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
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vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
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memory_region_add_subregion_overlap(address_space,
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isa_mem_base + 0x000a0000,
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0x000a0000,
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vga_io_memory,
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1);
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memory_region_set_coalescing(vga_io_memory);
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@ -208,7 +208,7 @@ static void pc_init1(MachineState *machine,
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} else {
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pci_bus = NULL;
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i440fx_state = NULL;
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isa_bus = isa_bus_new(NULL, system_io);
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isa_bus = isa_bus_new(NULL, get_system_memory(), system_io);
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no_hpet = 1;
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}
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isa_bus_irqs(isa_bus, gsi);
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@ -75,7 +75,8 @@ static int i82378_initfn(PCIDevice *pci)
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pci_config_set_interrupt_pin(pci_conf, 1); /* interrupt pin 0 */
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isabus = isa_bus_new(dev, pci_address_space_io(pci));
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isabus = isa_bus_new(dev, get_system_memory(),
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pci_address_space_io(pci));
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/* This device has:
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2 82C59 (irq)
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@ -21,10 +21,8 @@
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/isa/isa.h"
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#include "exec/address-spaces.h"
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static ISABus *isabus;
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hwaddr isa_mem_base = 0;
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static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static char *isabus_get_fw_dev_path(DeviceState *dev);
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@ -44,7 +42,8 @@ static const TypeInfo isa_bus_info = {
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.class_init = isa_bus_class_init,
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};
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ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io)
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ISABus *isa_bus_new(DeviceState *dev, MemoryRegion* address_space,
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MemoryRegion *address_space_io)
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{
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if (isabus) {
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fprintf(stderr, "Can't create a second ISA bus\n");
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@ -56,6 +55,7 @@ ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io)
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}
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isabus = ISA_BUS(qbus_create(TYPE_ISA_BUS, dev, NULL));
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isabus->address_space = address_space;
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isabus->address_space_io = address_space_io;
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return isabus;
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}
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@ -250,7 +250,11 @@ static char *isabus_get_fw_dev_path(DeviceState *dev)
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MemoryRegion *isa_address_space(ISADevice *dev)
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{
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return get_system_memory();
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if (dev) {
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return isa_bus_from_device(dev)->address_space;
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}
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return isabus->address_space;
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}
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MemoryRegion *isa_address_space_io(ISADevice *dev)
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@ -575,7 +575,7 @@ static int ich9_lpc_init(PCIDevice *d)
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ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
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ISABus *isa_bus;
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isa_bus = isa_bus_new(&d->qdev, get_system_io());
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isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io());
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pci_set_long(d->wmask + ICH9_LPC_PMBASE,
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ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
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@ -86,7 +86,8 @@ static int piix4_initfn(PCIDevice *dev)
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{
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PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
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isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
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isa_bus_new(DEVICE(d), pci_address_space(dev),
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pci_address_space_io(dev));
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piix4_dev = &d->dev;
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qemu_register_reset(piix4_reset, d);
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return 0;
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@ -429,7 +429,8 @@ static int vt82c686b_initfn(PCIDevice *d)
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uint8_t *wmask;
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int i;
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isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d));
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isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
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pci_address_space_io(d));
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pci_conf = d->config;
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pci_config_set_prog_interface(pci_conf, 0x0);
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@ -239,7 +239,11 @@ typedef struct GT64120State {
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uint32_t regs[GT_REGS];
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PCI_MAPPING_ENTRY(PCI0IO);
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PCI_MAPPING_ENTRY(PCI0M0);
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PCI_MAPPING_ENTRY(PCI0M1);
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PCI_MAPPING_ENTRY(ISD);
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MemoryRegion pci0_mem;
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AddressSpace pci0_mem_as;
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} GT64120State;
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/* Adjust range to avoid touching space which isn't mappable via PCI */
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@ -290,25 +294,63 @@ static void gt64120_isd_mapping(GT64120State *s)
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static void gt64120_pci_mapping(GT64120State *s)
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{
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/* Update IO mapping */
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if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
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{
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/* Unmap old IO address */
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if (s->PCI0IO_length)
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{
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memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
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object_unparent(OBJECT(&s->PCI0IO_mem));
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}
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/* Map new IO address */
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s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
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s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
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isa_mem_base = s->PCI0IO_start;
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if (s->PCI0IO_length) {
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memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio",
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get_system_io(), 0, s->PCI0IO_length);
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memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
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&s->PCI0IO_mem);
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}
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/* Update PCI0IO mapping */
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if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
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/* Unmap old IO address */
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if (s->PCI0IO_length) {
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memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
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object_unparent(OBJECT(&s->PCI0IO_mem));
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}
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/* Map new IO address */
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s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
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s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
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(s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
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if (s->PCI0IO_length) {
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memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
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get_system_io(), 0, s->PCI0IO_length);
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memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
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&s->PCI0IO_mem);
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}
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}
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/* Update PCI0M0 mapping */
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if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
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/* Unmap old MEM address */
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if (s->PCI0M0_length) {
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memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
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object_unparent(OBJECT(&s->PCI0M0_mem));
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}
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/* Map new mem address */
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s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
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s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
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(s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
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if (s->PCI0M0_length) {
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memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
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&s->pci0_mem, s->PCI0M0_start,
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s->PCI0M0_length);
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memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
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&s->PCI0M0_mem);
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}
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}
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/* Update PCI0M1 mapping */
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if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
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/* Unmap old MEM address */
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if (s->PCI0M1_length) {
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memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
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object_unparent(OBJECT(&s->PCI0M1_mem));
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}
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/* Map new mem address */
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s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
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s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
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(s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
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if (s->PCI0M1_length) {
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memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
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&s->pci0_mem, s->PCI0M1_start,
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s->PCI0M1_length);
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memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
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&s->PCI0M1_mem);
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}
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}
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}
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@ -363,10 +405,12 @@ static void gt64120_writel (void *opaque, hwaddr addr,
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case GT_PCI0M0LD:
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s->regs[GT_PCI0M0LD] = val & 0x00007fff;
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s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s);
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break;
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case GT_PCI0M1LD:
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s->regs[GT_PCI0M1LD] = val & 0x00007fff;
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s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
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gt64120_pci_mapping(s);
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break;
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case GT_PCI1IOLD:
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s->regs[GT_PCI1IOLD] = val & 0x00007fff;
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|
@ -380,12 +424,12 @@ static void gt64120_writel (void *opaque, hwaddr addr,
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s->regs[GT_PCI1M1LD] = val & 0x00007fff;
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s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
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break;
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case GT_PCI0M0HD:
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case GT_PCI0M1HD:
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case GT_PCI0IOHD:
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s->regs[saddr] = val & 0x0000007f;
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gt64120_pci_mapping(s);
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break;
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case GT_PCI0M0HD:
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case GT_PCI0M1HD:
|
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case GT_PCI1IOHD:
|
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case GT_PCI1M0HD:
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case GT_PCI1M1HD:
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|
@ -1124,10 +1168,12 @@ PCIBus *gt64120_register(qemu_irq *pic)
|
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qdev_init_nofail(dev);
|
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d = GT64120_PCI_HOST_BRIDGE(dev);
|
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phb = PCI_HOST_BRIDGE(dev);
|
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memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);
|
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address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
|
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phb->bus = pci_register_bus(dev, "pci",
|
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gt64120_pci_set_irq, gt64120_pci_map_irq,
|
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pic,
|
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get_system_memory(),
|
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&d->pci0_mem,
|
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get_system_io(),
|
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PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
|
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memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
|
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|
@ -1142,11 +1188,6 @@ static int gt64120_init(SysBusDevice *dev)
|
|||
|
||||
s = GT64120_PCI_HOST_BRIDGE(dev);
|
||||
|
||||
/* FIXME: This value is computed from registers during reset, but some
|
||||
devices (e.g. VGA card) need to know it when they are registered.
|
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This also mean that changing the register to change the mapping
|
||||
does not fully work. */
|
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isa_mem_base = 0x10000000;
|
||||
qemu_register_reset(gt64120_reset, s);
|
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return 0;
|
||||
}
|
||||
|
|
|
@ -60,13 +60,16 @@ static void main_cpu_reset(void *opaque)
|
|||
|
||||
static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
|
||||
{
|
||||
return cpu_inw(0x71);
|
||||
uint8_t val;
|
||||
address_space_read(&address_space_memory, 0x90000071, &val, 1);
|
||||
return val;
|
||||
}
|
||||
|
||||
static void rtc_write(void *opaque, hwaddr addr,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
cpu_outw(0x71, val & 0xff);
|
||||
uint8_t buf = val & 0xff;
|
||||
address_space_write(&address_space_memory, 0x90000071, &buf, 1);
|
||||
}
|
||||
|
||||
static const MemoryRegionOps rtc_ops = {
|
||||
|
@ -120,12 +123,11 @@ static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
|
|||
(*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
|
||||
}
|
||||
|
||||
static void mips_jazz_init(MemoryRegion *address_space,
|
||||
MemoryRegion *address_space_io,
|
||||
ram_addr_t ram_size,
|
||||
const char *cpu_model,
|
||||
static void mips_jazz_init(MachineState *machine,
|
||||
enum jazz_model_e jazz_model)
|
||||
{
|
||||
MemoryRegion *address_space = get_system_memory();
|
||||
const char *cpu_model = machine->cpu_model;
|
||||
char *filename;
|
||||
int bios_size, n;
|
||||
MIPSCPU *cpu;
|
||||
|
@ -134,7 +136,8 @@ static void mips_jazz_init(MemoryRegion *address_space,
|
|||
qemu_irq *rc4030, *i8259;
|
||||
rc4030_dma *dmas;
|
||||
void* rc4030_opaque;
|
||||
MemoryRegion *isa = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *rtc = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
|
||||
|
@ -179,7 +182,8 @@ static void mips_jazz_init(MemoryRegion *address_space,
|
|||
cc->do_unassigned_access = mips_jazz_do_unassigned_access;
|
||||
|
||||
/* allocate RAM */
|
||||
memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size, &error_abort);
|
||||
memory_region_init_ram(ram, NULL, "mips_jazz.ram", machine->ram_size,
|
||||
&error_abort);
|
||||
vmstate_register_ram_global(ram);
|
||||
memory_region_add_subregion(address_space, 0, ram);
|
||||
|
||||
|
@ -218,8 +222,14 @@ static void mips_jazz_init(MemoryRegion *address_space,
|
|||
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
|
||||
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
|
||||
|
||||
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
|
||||
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
|
||||
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
|
||||
memory_region_add_subregion(address_space, 0x90000000, isa_io);
|
||||
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
|
||||
isa_bus = isa_bus_new(NULL, isa_mem, isa_io);
|
||||
|
||||
/* ISA devices */
|
||||
isa_bus = isa_bus_new(NULL, address_space_io);
|
||||
i8259 = i8259_init(isa_bus, env->irq[4]);
|
||||
isa_bus_irqs(isa_bus, i8259);
|
||||
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
|
||||
|
@ -227,12 +237,6 @@ static void mips_jazz_init(MemoryRegion *address_space,
|
|||
pit = pit_init(isa_bus, 0x40, 0, NULL);
|
||||
pcspk_init(isa_bus, pit);
|
||||
|
||||
/* ISA IO space at 0x90000000 */
|
||||
memory_region_init_alias(isa, NULL, "isa_mmio",
|
||||
get_system_io(), 0, 0x01000000);
|
||||
memory_region_add_subregion(address_space, 0x90000000, isa);
|
||||
isa_mem_base = 0x11000000;
|
||||
|
||||
/* Video card */
|
||||
switch (jazz_model) {
|
||||
case JAZZ_MAGNUM:
|
||||
|
@ -333,19 +337,13 @@ static void mips_jazz_init(MemoryRegion *address_space,
|
|||
static
|
||||
void mips_magnum_init(MachineState *machine)
|
||||
{
|
||||
ram_addr_t ram_size = machine->ram_size;
|
||||
const char *cpu_model = machine->cpu_model;
|
||||
mips_jazz_init(get_system_memory(), get_system_io(),
|
||||
ram_size, cpu_model, JAZZ_MAGNUM);
|
||||
mips_jazz_init(machine, JAZZ_MAGNUM);
|
||||
}
|
||||
|
||||
static
|
||||
void mips_pica61_init(MachineState *machine)
|
||||
{
|
||||
ram_addr_t ram_size = machine->ram_size;
|
||||
const char *cpu_model = machine->cpu_model;
|
||||
mips_jazz_init(get_system_memory(), get_system_io(),
|
||||
ram_size, cpu_model, JAZZ_PICA61);
|
||||
mips_jazz_init(machine, JAZZ_PICA61);
|
||||
}
|
||||
|
||||
static QEMUMachine mips_magnum_machine = {
|
||||
|
|
|
@ -165,7 +165,8 @@ void mips_r4k_init(MachineState *machine)
|
|||
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *bios;
|
||||
MemoryRegion *iomem = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *isa = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
|
||||
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
|
||||
int bios_size;
|
||||
MIPSCPU *cpu;
|
||||
CPUMIPSState *env;
|
||||
|
@ -267,20 +268,20 @@ void mips_r4k_init(MachineState *machine)
|
|||
cpu_mips_irq_init_cpu(env);
|
||||
cpu_mips_clock_init(env);
|
||||
|
||||
/* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
|
||||
memory_region_init_alias(isa_io, NULL, "isa-io",
|
||||
get_system_io(), 0, 0x00010000);
|
||||
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
|
||||
memory_region_add_subregion(get_system_memory(), 0x14000000, isa_io);
|
||||
memory_region_add_subregion(get_system_memory(), 0x10000000, isa_mem);
|
||||
isa_bus = isa_bus_new(NULL, isa_mem, get_system_io());
|
||||
|
||||
/* The PIC is attached to the MIPS CPU INT0 pin */
|
||||
isa_bus = isa_bus_new(NULL, get_system_io());
|
||||
i8259 = i8259_init(isa_bus, env->irq[2]);
|
||||
isa_bus_irqs(isa_bus, i8259);
|
||||
|
||||
rtc_init(isa_bus, 2000, NULL);
|
||||
|
||||
/* Register 64 KB of ISA IO space at 0x14000000 */
|
||||
memory_region_init_alias(isa, NULL, "isa_mmio",
|
||||
get_system_io(), 0, 0x00010000);
|
||||
memory_region_add_subregion(get_system_memory(), 0x14000000, isa);
|
||||
|
||||
isa_mem_base = 0x10000000;
|
||||
|
||||
pit = pit_init(isa_bus, 0x40, 0, NULL);
|
||||
|
||||
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
|
||||
|
|
|
@ -635,7 +635,8 @@ static int piix3_initfn(PCIDevice *dev)
|
|||
{
|
||||
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
|
||||
|
||||
isa_bus_new(DEVICE(d), pci_address_space_io(dev));
|
||||
isa_bus_new(DEVICE(d), get_system_memory(),
|
||||
pci_address_space_io(dev));
|
||||
|
||||
memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
|
||||
"piix3-reset-control", 1);
|
||||
|
|
|
@ -596,7 +596,8 @@ pci_ebus_init1(PCIDevice *pci_dev)
|
|||
{
|
||||
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
|
||||
|
||||
isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
|
||||
isa_bus_new(DEVICE(pci_dev), get_system_memory(),
|
||||
pci_address_space_io(pci_dev));
|
||||
|
||||
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
|
||||
pci_dev->config[0x05] = 0x00;
|
||||
|
|
|
@ -36,6 +36,7 @@ struct ISABus {
|
|||
BusState parent_obj;
|
||||
/*< public >*/
|
||||
|
||||
MemoryRegion *address_space;
|
||||
MemoryRegion *address_space_io;
|
||||
qemu_irq *irqs;
|
||||
};
|
||||
|
@ -50,7 +51,8 @@ struct ISADevice {
|
|||
int ioport_id;
|
||||
};
|
||||
|
||||
ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space_io);
|
||||
ISABus *isa_bus_new(DeviceState *dev, MemoryRegion *address_space,
|
||||
MemoryRegion *address_space_io);
|
||||
void isa_bus_irqs(ISABus *bus, qemu_irq *irqs);
|
||||
qemu_irq isa_get_irq(ISADevice *dev, int isairq);
|
||||
void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq);
|
||||
|
@ -97,8 +99,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
|
|||
return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
|
||||
}
|
||||
|
||||
extern hwaddr isa_mem_base;
|
||||
|
||||
/* dma.c */
|
||||
int DMA_get_channel_mode (int nchan);
|
||||
int DMA_read_memory (int nchan, void *buf, int pos, int size);
|
||||
|
|
|
@ -1607,73 +1607,25 @@ struct target_stat {
|
|||
#elif defined(TARGET_ABI_MIPSN32)
|
||||
|
||||
struct target_stat {
|
||||
unsigned st_dev;
|
||||
int st_pad1[3]; /* Reserved for network id */
|
||||
unsigned int st_ino;
|
||||
unsigned int st_mode;
|
||||
unsigned int st_nlink;
|
||||
int st_uid;
|
||||
int st_gid;
|
||||
unsigned st_rdev;
|
||||
unsigned int st_pad2[2];
|
||||
unsigned int st_size;
|
||||
unsigned int st_pad3;
|
||||
/*
|
||||
* Actually this should be timestruc_t st_atime, st_mtime and st_ctime
|
||||
* but we don't have it under Linux.
|
||||
*/
|
||||
unsigned int target_st_atime;
|
||||
unsigned int target_st_atime_nsec;
|
||||
unsigned int target_st_mtime;
|
||||
unsigned int target_st_mtime_nsec;
|
||||
unsigned int target_st_ctime;
|
||||
unsigned int target_st_ctime_nsec;
|
||||
unsigned int st_blksize;
|
||||
unsigned int st_blocks;
|
||||
unsigned int st_pad4[14];
|
||||
};
|
||||
|
||||
/*
|
||||
* This matches struct stat64 in glibc2.1, hence the absolutely insane
|
||||
* amounts of padding around dev_t's. The memory layout is the same as of
|
||||
* struct stat of the 64-bit kernel.
|
||||
*/
|
||||
|
||||
#define TARGET_HAS_STRUCT_STAT64
|
||||
struct target_stat64 {
|
||||
unsigned int st_dev;
|
||||
unsigned int st_pad0[3]; /* Reserved for st_dev expansion */
|
||||
|
||||
target_ulong st_ino;
|
||||
|
||||
unsigned int st_mode;
|
||||
unsigned int st_nlink;
|
||||
|
||||
int st_uid;
|
||||
int st_gid;
|
||||
|
||||
unsigned int st_rdev;
|
||||
unsigned int st_pad1[3]; /* Reserved for st_rdev expansion */
|
||||
|
||||
int st_size;
|
||||
|
||||
/*
|
||||
* Actually this should be timestruc_t st_atime, st_mtime and st_ctime
|
||||
* but we don't have it under Linux.
|
||||
*/
|
||||
int target_st_atime;
|
||||
unsigned int target_st_atime_nsec; /* Reserved for st_atime expansion */
|
||||
|
||||
int target_st_mtime;
|
||||
unsigned int target_st_mtime_nsec; /* Reserved for st_mtime expansion */
|
||||
|
||||
int target_st_ctime;
|
||||
unsigned int target_st_ctime_nsec; /* Reserved for st_ctime expansion */
|
||||
|
||||
unsigned int st_blksize;
|
||||
unsigned int st_pad2;
|
||||
|
||||
int st_blocks;
|
||||
abi_ulong st_dev;
|
||||
abi_ulong st_pad0[3]; /* Reserved for st_dev expansion */
|
||||
uint64_t st_ino;
|
||||
unsigned int st_mode;
|
||||
unsigned int st_nlink;
|
||||
int st_uid;
|
||||
int st_gid;
|
||||
abi_ulong st_rdev;
|
||||
abi_ulong st_pad1[3]; /* Reserved for st_rdev expansion */
|
||||
int64_t st_size;
|
||||
abi_long target_st_atime;
|
||||
abi_ulong target_st_atime_nsec; /* Reserved for st_atime expansion */
|
||||
abi_long target_st_mtime;
|
||||
abi_ulong target_st_mtime_nsec; /* Reserved for st_mtime expansion */
|
||||
abi_long target_st_ctime;
|
||||
abi_ulong target_st_ctime_nsec; /* Reserved for st_ctime expansion */
|
||||
abi_ulong st_blksize;
|
||||
abi_ulong st_pad2;
|
||||
int64_t st_blocks;
|
||||
};
|
||||
|
||||
#elif defined(TARGET_ABI_MIPSO32)
|
||||
|
|
|
@ -285,6 +285,10 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
|
|||
qemu_get_sbe32s(f, &env->CP0_SRSConf4);
|
||||
qemu_get_sbe32s(f, &env->CP0_HWREna);
|
||||
qemu_get_betls(f, &env->CP0_BadVAddr);
|
||||
if (version_id >= 5) {
|
||||
qemu_get_be32s(f, &env->CP0_BadInstr);
|
||||
qemu_get_be32s(f, &env->CP0_BadInstrP);
|
||||
}
|
||||
qemu_get_sbe32s(f, &env->CP0_Count);
|
||||
qemu_get_betls(f, &env->CP0_EntryHi);
|
||||
qemu_get_sbe32s(f, &env->CP0_Compare);
|
||||
|
@ -319,8 +323,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
|
|||
qemu_get_betls(f, &env->CP0_ErrorEPC);
|
||||
qemu_get_sbe32s(f, &env->CP0_DESAVE);
|
||||
if (version_id >= 5) {
|
||||
qemu_get_be32s(f, &env->CP0_BadInstr);
|
||||
qemu_get_be32s(f, &env->CP0_BadInstrP);
|
||||
for (i = 0; i < MIPS_KSCRATCH_NUM; i++) {
|
||||
qemu_get_betls(f, &env->CP0_KScratch[i]);
|
||||
}
|
||||
|
|
|
@ -304,16 +304,20 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
|
|||
}
|
||||
}
|
||||
|
||||
#define HELPER_LD_ATOMIC(name, insn) \
|
||||
#define HELPER_LD_ATOMIC(name, insn, almask) \
|
||||
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
|
||||
{ \
|
||||
if (arg & almask) { \
|
||||
env->CP0_BadVAddr = arg; \
|
||||
helper_raise_exception(env, EXCP_AdEL); \
|
||||
} \
|
||||
env->lladdr = do_translate_address(env, arg, 0); \
|
||||
env->llval = do_##insn(env, arg, mem_idx); \
|
||||
return env->llval; \
|
||||
}
|
||||
HELPER_LD_ATOMIC(ll, lw)
|
||||
HELPER_LD_ATOMIC(ll, lw, 0x3)
|
||||
#ifdef TARGET_MIPS64
|
||||
HELPER_LD_ATOMIC(lld, ld)
|
||||
HELPER_LD_ATOMIC(lld, ld, 0x7)
|
||||
#endif
|
||||
#undef HELPER_LD_ATOMIC
|
||||
|
||||
|
|
|
@ -4947,7 +4947,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
#if defined(TARGET_MIPS64)
|
||||
if (ctx->rxi) {
|
||||
TCGv tmp = tcg_temp_new();
|
||||
tcg_gen_andi_tl(tmp, arg, (3ull << 62));
|
||||
tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
|
||||
tcg_gen_shri_tl(tmp, tmp, 32);
|
||||
tcg_gen_or_tl(arg, arg, tmp);
|
||||
tcg_temp_free(tmp);
|
||||
|
@ -5002,7 +5002,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
|
|||
#if defined(TARGET_MIPS64)
|
||||
if (ctx->rxi) {
|
||||
TCGv tmp = tcg_temp_new();
|
||||
tcg_gen_andi_tl(tmp, arg, (3ull << 62));
|
||||
tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI));
|
||||
tcg_gen_shri_tl(tmp, tmp, 32);
|
||||
tcg_gen_or_tl(arg, arg, tmp);
|
||||
tcg_temp_free(tmp);
|
||||
|
@ -13653,7 +13653,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
|
|||
target. */
|
||||
break;
|
||||
case LUI:
|
||||
gen_logic_imm(ctx, OPC_LUI, rs, -1, imm);
|
||||
gen_logic_imm(ctx, OPC_LUI, rs, 0, imm);
|
||||
break;
|
||||
case SYNCI:
|
||||
/* Break the TB to be able to sync copied instructions
|
||||
|
@ -19095,6 +19095,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
|||
CPUMIPSState *env = &cpu->env;
|
||||
DisasContext ctx;
|
||||
target_ulong pc_start;
|
||||
target_ulong next_page_start;
|
||||
CPUBreakpoint *bp;
|
||||
int j, lj = -1;
|
||||
int num_insns;
|
||||
|
@ -19106,6 +19107,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
|||
qemu_log("search pc %d\n", search_pc);
|
||||
|
||||
pc_start = tb->pc;
|
||||
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
|
||||
ctx.pc = pc_start;
|
||||
ctx.saved_pc = -1;
|
||||
ctx.singlestep_enabled = cs->singlestep_enabled;
|
||||
|
@ -19204,8 +19206,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
|
|||
break;
|
||||
}
|
||||
|
||||
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
|
||||
if (ctx.pc >= next_page_start) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (tcg_op_buf_full()) {
|
||||
break;
|
||||
|
|
|
@ -474,7 +474,7 @@ static const mips_def_t mips_defs[] =
|
|||
.CP0_LLAddr_shift = 4,
|
||||
.SYNCI_Step = 32,
|
||||
.CCRes = 2,
|
||||
.CP0_Status_rw_bitmask = 0x32F8FFFF,
|
||||
.CP0_Status_rw_bitmask = 0x12F8FFFF,
|
||||
.SEGBITS = 42,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS64,
|
||||
|
@ -575,7 +575,7 @@ static const mips_def_t mips_defs[] =
|
|||
.CP0_LLAddr_shift = 4,
|
||||
.SYNCI_Step = 32,
|
||||
.CCRes = 2,
|
||||
.CP0_Status_rw_bitmask = 0x32F8FFFF,
|
||||
.CP0_Status_rw_bitmask = 0x12F8FFFF,
|
||||
.SEGBITS = 42,
|
||||
.PABITS = 36,
|
||||
.insn_flags = CPU_MIPS64R2,
|
||||
|
|
Loading…
Reference in a new issue