xics: rename types to be sane and follow coding style
Basically, in HW the layout of the interrupt network is:
- One ICP per processor thread (the "presenter"). This contains the
registers to fetch a pending interrupt (ack), EOI, and control the
processor priority.
- One ICS per logical source of interrupts (ie, one per PCI host
bridge, and a few others here or there). This contains the per-interrupt
source configuration (target processor(s), priority, mask) and the
per-interrupt internal state.
Under PAPR, there is a single "virtual" ICS ... somewhat (it's a bit
oddball what pHyp does here, arguably there are two but we can ignore
that distinction). There is no register level access. A pair of firmware
(RTAS) calls is used to configure each virtual interrupt.
So our model here is somewhat the same. We have one ICS in the emulated
XICS which arguably *is* the emulated XICS, there's no point making it a
separate "device", that would just be gross, and each VCPU has an
associated ICP.
Yet we call the "XICS" struct icp_state and then the ICPs
'struct icp_server_state'. It's particularly confusing when all of the
functions have xics_prefixes yet take *icp arguments.
Rename:
struct icp_state -> XICSState
struct icp_server_state -> ICPState
struct ics_state -> ICSState
struct ics_irq_state -> ICSIRQState
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-id: 1374175984-8930-12-git-send-email-aliguori@us.ibm.com
[aik: added ics_resend() on post_load]
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori
parent
e68cb8b4fa
commit
c04d6cfa3f
349
hw/intc/xics.c
349
hw/intc/xics.c
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@ -34,34 +34,19 @@
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* ICP: Presentation layer
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*/
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struct icp_server_state {
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uint32_t xirr;
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uint8_t pending_priority;
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uint8_t mfrr;
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qemu_irq output;
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};
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#define XISR_MASK 0x00ffffff
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#define CPPR_MASK 0xff000000
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#define XISR(ss) (((ss)->xirr) & XISR_MASK)
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#define CPPR(ss) (((ss)->xirr) >> 24)
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struct ics_state;
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static void ics_reject(ICSState *ics, int nr);
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static void ics_resend(ICSState *ics);
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static void ics_eoi(ICSState *ics, int nr);
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struct icp_state {
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long nr_servers;
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struct icp_server_state *ss;
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struct ics_state *ics;
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};
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static void ics_reject(struct ics_state *ics, int nr);
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static void ics_resend(struct ics_state *ics);
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static void ics_eoi(struct ics_state *ics, int nr);
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static void icp_check_ipi(struct icp_state *icp, int server)
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static void icp_check_ipi(XICSState *icp, int server)
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{
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struct icp_server_state *ss = icp->ss + server;
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ICPState *ss = icp->ss + server;
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if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
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return;
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@ -78,9 +63,9 @@ static void icp_check_ipi(struct icp_state *icp, int server)
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qemu_irq_raise(ss->output);
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}
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static void icp_resend(struct icp_state *icp, int server)
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static void icp_resend(XICSState *icp, int server)
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{
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struct icp_server_state *ss = icp->ss + server;
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ICPState *ss = icp->ss + server;
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if (ss->mfrr < CPPR(ss)) {
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icp_check_ipi(icp, server);
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@ -88,9 +73,9 @@ static void icp_resend(struct icp_state *icp, int server)
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ics_resend(icp->ics);
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}
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static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
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static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
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{
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struct icp_server_state *ss = icp->ss + server;
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ICPState *ss = icp->ss + server;
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uint8_t old_cppr;
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uint32_t old_xisr;
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@ -112,9 +97,9 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
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}
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}
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static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
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static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
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{
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struct icp_server_state *ss = icp->ss + server;
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ICPState *ss = icp->ss + server;
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ss->mfrr = mfrr;
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if (mfrr < CPPR(ss)) {
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@ -122,7 +107,7 @@ static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr)
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}
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}
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static uint32_t icp_accept(struct icp_server_state *ss)
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static uint32_t icp_accept(ICPState *ss)
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{
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uint32_t xirr = ss->xirr;
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@ -135,9 +120,9 @@ static uint32_t icp_accept(struct icp_server_state *ss)
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return xirr;
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}
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static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
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static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
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{
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struct icp_server_state *ss = icp->ss + server;
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ICPState *ss = icp->ss + server;
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/* Send EOI -> ICS */
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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@ -148,9 +133,9 @@ static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
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}
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}
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static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
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static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
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{
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struct icp_server_state *ss = icp->ss + server;
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ICPState *ss = icp->ss + server;
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trace_xics_icp_irq(server, nr, priority);
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@ -168,39 +153,59 @@ static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
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}
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}
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static const VMStateDescription vmstate_icp_server = {
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.name = "icp/server",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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/* Sanity check */
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VMSTATE_UINT32(xirr, ICPState),
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VMSTATE_UINT8(pending_priority, ICPState),
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VMSTATE_UINT8(mfrr, ICPState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void icp_reset(DeviceState *dev)
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{
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ICPState *icp = ICP(dev);
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icp->xirr = 0;
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icp->pending_priority = 0xff;
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icp->mfrr = 0xff;
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/* Make all outputs are deasserted */
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qemu_set_irq(icp->output, 0);
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}
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static void icp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = icp_reset;
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dc->vmsd = &vmstate_icp_server;
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}
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static TypeInfo icp_info = {
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.name = TYPE_ICP,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(ICPState),
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.class_init = icp_class_init,
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};
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/*
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* ICS: Source layer
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*/
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struct ics_irq_state {
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int server;
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uint8_t priority;
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uint8_t saved_priority;
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#define XICS_STATUS_ASSERTED 0x1
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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uint8_t status;
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};
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struct ics_state {
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int nr_irqs;
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int offset;
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qemu_irq *qirqs;
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bool *islsi;
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struct ics_irq_state *irqs;
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struct icp_state *icp;
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};
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static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
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static int ics_valid_irq(ICSState *ics, uint32_t nr)
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{
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return (nr >= ics->offset)
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&& (nr < (ics->offset + ics->nr_irqs));
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}
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static void resend_msi(struct ics_state *ics, int srcno)
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static void resend_msi(ICSState *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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/* FIXME: filter by server#? */
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if (irq->status & XICS_STATUS_REJECTED) {
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@ -212,9 +217,9 @@ static void resend_msi(struct ics_state *ics, int srcno)
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}
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}
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static void resend_lsi(struct ics_state *ics, int srcno)
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static void resend_lsi(ICSState *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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if ((irq->priority != 0xff)
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&& (irq->status & XICS_STATUS_ASSERTED)
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@ -224,9 +229,9 @@ static void resend_lsi(struct ics_state *ics, int srcno)
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}
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}
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static void set_irq_msi(struct ics_state *ics, int srcno, int val)
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static void set_irq_msi(ICSState *ics, int srcno, int val)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_set_irq_msi(srcno, srcno + ics->offset);
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@ -240,9 +245,9 @@ static void set_irq_msi(struct ics_state *ics, int srcno, int val)
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}
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}
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static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
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static void set_irq_lsi(ICSState *ics, int srcno, int val)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
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if (val) {
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@ -255,7 +260,7 @@ static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
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static void ics_set_irq(void *opaque, int srcno, int val)
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{
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struct ics_state *ics = (struct ics_state *)opaque;
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ICSState *ics = (ICSState *)opaque;
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if (ics->islsi[srcno]) {
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set_irq_lsi(ics, srcno, val);
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@ -264,9 +269,9 @@ static void ics_set_irq(void *opaque, int srcno, int val)
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}
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}
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static void write_xive_msi(struct ics_state *ics, int srcno)
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static void write_xive_msi(ICSState *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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if (!(irq->status & XICS_STATUS_MASKED_PENDING)
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|| (irq->priority == 0xff)) {
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@ -277,16 +282,16 @@ static void write_xive_msi(struct ics_state *ics, int srcno)
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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static void write_xive_lsi(struct ics_state *ics, int srcno)
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static void write_xive_lsi(ICSState *ics, int srcno)
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{
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resend_lsi(ics, srcno);
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}
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static void ics_write_xive(struct ics_state *ics, int nr, int server,
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static void ics_write_xive(ICSState *ics, int nr, int server,
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uint8_t priority, uint8_t saved_priority)
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{
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int srcno = nr - ics->offset;
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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irq->server = server;
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irq->priority = priority;
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@ -301,16 +306,16 @@ static void ics_write_xive(struct ics_state *ics, int nr, int server,
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}
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}
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static void ics_reject(struct ics_state *ics, int nr)
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static void ics_reject(ICSState *ics, int nr)
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{
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struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
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ICSIRQState *irq = ics->irqs + nr - ics->offset;
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trace_xics_ics_reject(nr, nr - ics->offset);
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irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
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irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
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}
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static void ics_resend(struct ics_state *ics)
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static void ics_resend(ICSState *ics)
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{
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int i;
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@ -324,10 +329,10 @@ static void ics_resend(struct ics_state *ics)
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}
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}
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static void ics_eoi(struct ics_state *ics, int nr)
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static void ics_eoi(ICSState *ics, int nr)
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{
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int srcno = nr - ics->offset;
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struct ics_irq_state *irq = ics->irqs + srcno;
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_ics_eoi(nr);
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@ -336,11 +341,92 @@ static void ics_eoi(struct ics_state *ics, int nr)
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}
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}
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static void ics_reset(DeviceState *dev)
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{
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ICSState *ics = ICS(dev);
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int i;
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memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
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for (i = 0; i < ics->nr_irqs; i++) {
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ics->irqs[i].priority = 0xff;
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ics->irqs[i].saved_priority = 0xff;
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}
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}
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static int ics_post_load(void *opaque, int version_id)
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{
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int i;
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ICSState *ics = opaque;
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for (i = 0; i < ics->icp->nr_servers; i++) {
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icp_resend(ics->icp, i);
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}
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return 0;
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}
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static const VMStateDescription vmstate_ics_irq = {
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.name = "ics/irq",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(server, ICSIRQState),
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VMSTATE_UINT8(priority, ICSIRQState),
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VMSTATE_UINT8(saved_priority, ICSIRQState),
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VMSTATE_UINT8(status, ICSIRQState),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_ics = {
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.name = "ics",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = ics_post_load,
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.fields = (VMStateField []) {
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/* Sanity check */
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VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
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VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
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vmstate_ics_irq, ICSIRQState),
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VMSTATE_END_OF_LIST()
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},
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};
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static int ics_realize(DeviceState *dev)
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{
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ICSState *ics = ICS(dev);
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ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
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ics->islsi = g_malloc0(ics->nr_irqs * sizeof(bool));
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ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
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return 0;
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}
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static void ics_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->init = ics_realize;
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dc->vmsd = &vmstate_ics;
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dc->reset = ics_reset;
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}
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static TypeInfo ics_info = {
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.name = TYPE_ICS,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(ICSState),
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.class_init = ics_class_init,
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};
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/*
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* Exported functions
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*/
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qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
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qemu_irq xics_get_qirq(XICSState *icp, int irq)
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{
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if (!ics_valid_irq(icp->ics, irq)) {
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return NULL;
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@ -349,13 +435,17 @@ qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
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return icp->ics->qirqs[irq - icp->ics->offset];
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}
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void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi)
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void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
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{
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assert(ics_valid_irq(icp->ics, irq));
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|
||||
icp->ics->islsi[irq - icp->ics->offset] = lsi;
|
||||
}
|
||||
|
||||
/*
|
||||
* Guest interfaces
|
||||
*/
|
||||
|
||||
static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
||||
target_ulong opcode, target_ulong *args)
|
||||
{
|
||||
|
|
@ -405,7 +495,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|||
uint32_t nargs, target_ulong args,
|
||||
uint32_t nret, target_ulong rets)
|
||||
{
|
||||
struct ics_state *ics = spapr->icp->ics;
|
||||
ICSState *ics = spapr->icp->ics;
|
||||
uint32_t nr, server, priority;
|
||||
|
||||
if ((nargs != 3) || (nret != 1)) {
|
||||
|
|
@ -433,7 +523,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|||
uint32_t nargs, target_ulong args,
|
||||
uint32_t nret, target_ulong rets)
|
||||
{
|
||||
struct ics_state *ics = spapr->icp->ics;
|
||||
ICSState *ics = spapr->icp->ics;
|
||||
uint32_t nr;
|
||||
|
||||
if ((nargs != 1) || (nret != 3)) {
|
||||
|
|
@ -458,7 +548,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|||
uint32_t nargs, target_ulong args,
|
||||
uint32_t nret, target_ulong rets)
|
||||
{
|
||||
struct ics_state *ics = spapr->icp->ics;
|
||||
ICSState *ics = spapr->icp->ics;
|
||||
uint32_t nr;
|
||||
|
||||
if ((nargs != 1) || (nret != 1)) {
|
||||
|
|
@ -484,7 +574,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|||
uint32_t nargs, target_ulong args,
|
||||
uint32_t nret, target_ulong rets)
|
||||
{
|
||||
struct ics_state *ics = spapr->icp->ics;
|
||||
ICSState *ics = spapr->icp->ics;
|
||||
uint32_t nr;
|
||||
|
||||
if ((nargs != 1) || (nret != 1)) {
|
||||
|
|
@ -506,32 +596,27 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr,
|
|||
rtas_st(rets, 0, 0); /* Success */
|
||||
}
|
||||
|
||||
static void xics_reset(void *opaque)
|
||||
/*
|
||||
* XICS
|
||||
*/
|
||||
|
||||
static void xics_reset(DeviceState *d)
|
||||
{
|
||||
struct icp_state *icp = (struct icp_state *)opaque;
|
||||
struct ics_state *ics = icp->ics;
|
||||
XICSState *icp = XICS(d);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < icp->nr_servers; i++) {
|
||||
icp->ss[i].xirr = 0;
|
||||
icp->ss[i].pending_priority = 0xff;
|
||||
icp->ss[i].mfrr = 0xff;
|
||||
/* Make all outputs are deasserted */
|
||||
qemu_set_irq(icp->ss[i].output, 0);
|
||||
device_reset(DEVICE(&icp->ss[i]));
|
||||
}
|
||||
|
||||
memset(ics->irqs, 0, sizeof(struct ics_irq_state) * ics->nr_irqs);
|
||||
for (i = 0; i < ics->nr_irqs; i++) {
|
||||
ics->irqs[i].priority = 0xff;
|
||||
ics->irqs[i].saved_priority = 0xff;
|
||||
}
|
||||
device_reset(DEVICE(icp->ics));
|
||||
}
|
||||
|
||||
void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
|
||||
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
CPUPPCState *env = &cpu->env;
|
||||
struct icp_server_state *ss = &icp->ss[cs->cpu_index];
|
||||
ICPState *ss = &icp->ss[cs->cpu_index];
|
||||
|
||||
assert(cs->cpu_index < icp->nr_servers);
|
||||
|
||||
|
|
@ -551,37 +636,73 @@ void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu)
|
|||
}
|
||||
}
|
||||
|
||||
struct icp_state *xics_system_init(int nr_servers, int nr_irqs)
|
||||
static void xics_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
struct icp_state *icp;
|
||||
struct ics_state *ics;
|
||||
XICSState *icp = XICS(dev);
|
||||
ICSState *ics = icp->ics;
|
||||
int i;
|
||||
|
||||
icp = g_malloc0(sizeof(*icp));
|
||||
icp->nr_servers = nr_servers;
|
||||
icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
|
||||
|
||||
ics = g_malloc0(sizeof(*ics));
|
||||
ics->nr_irqs = nr_irqs;
|
||||
ics->nr_irqs = icp->nr_irqs;
|
||||
ics->offset = XICS_IRQ_BASE;
|
||||
ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
|
||||
ics->islsi = g_malloc0(nr_irqs * sizeof(bool));
|
||||
|
||||
icp->ics = ics;
|
||||
ics->icp = icp;
|
||||
qdev_init_nofail(DEVICE(ics));
|
||||
|
||||
ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
|
||||
icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
|
||||
for (i = 0; i < icp->nr_servers; i++) {
|
||||
char buffer[32];
|
||||
object_initialize(&icp->ss[i], TYPE_ICP);
|
||||
snprintf(buffer, sizeof(buffer), "icp[%d]", i);
|
||||
object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), NULL);
|
||||
qdev_init_nofail(DEVICE(&icp->ss[i]));
|
||||
}
|
||||
}
|
||||
|
||||
spapr_register_hypercall(H_CPPR, h_cppr);
|
||||
spapr_register_hypercall(H_IPI, h_ipi);
|
||||
spapr_register_hypercall(H_XIRR, h_xirr);
|
||||
spapr_register_hypercall(H_EOI, h_eoi);
|
||||
static void xics_initfn(Object *obj)
|
||||
{
|
||||
XICSState *xics = XICS(obj);
|
||||
|
||||
xics->ics = ICS(object_new(TYPE_ICS));
|
||||
object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
|
||||
}
|
||||
|
||||
static Property xics_properties[] = {
|
||||
DEFINE_PROP_UINT32("nr_servers", XICSState, nr_servers, -1),
|
||||
DEFINE_PROP_UINT32("nr_irqs", XICSState, nr_irqs, -1),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void xics_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(oc);
|
||||
|
||||
dc->realize = xics_realize;
|
||||
dc->props = xics_properties;
|
||||
dc->reset = xics_reset;
|
||||
|
||||
spapr_rtas_register("ibm,set-xive", rtas_set_xive);
|
||||
spapr_rtas_register("ibm,get-xive", rtas_get_xive);
|
||||
spapr_rtas_register("ibm,int-off", rtas_int_off);
|
||||
spapr_rtas_register("ibm,int-on", rtas_int_on);
|
||||
|
||||
qemu_register_reset(xics_reset, icp);
|
||||
|
||||
return icp;
|
||||
spapr_register_hypercall(H_CPPR, h_cppr);
|
||||
spapr_register_hypercall(H_IPI, h_ipi);
|
||||
spapr_register_hypercall(H_XIRR, h_xirr);
|
||||
spapr_register_hypercall(H_EOI, h_eoi);
|
||||
}
|
||||
|
||||
static const TypeInfo xics_info = {
|
||||
.name = TYPE_XICS,
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(XICSState),
|
||||
.class_init = xics_class_init,
|
||||
.instance_init = xics_initfn,
|
||||
};
|
||||
|
||||
static void xics_register_types(void)
|
||||
{
|
||||
type_register_static(&xics_info);
|
||||
type_register_static(&ics_info);
|
||||
type_register_static(&icp_info);
|
||||
}
|
||||
|
||||
type_init(xics_register_types)
|
||||
|
|
|
|||
|
|
@ -129,6 +129,34 @@ int spapr_allocate_irq_block(int num, bool lsi)
|
|||
return first;
|
||||
}
|
||||
|
||||
static XICSState *try_create_xics(const char *type, int nr_servers,
|
||||
int nr_irqs)
|
||||
{
|
||||
DeviceState *dev;
|
||||
|
||||
dev = qdev_create(NULL, type);
|
||||
qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
|
||||
qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
|
||||
if (qdev_init(dev) < 0) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return XICS(dev);
|
||||
}
|
||||
|
||||
static XICSState *xics_system_init(int nr_servers, int nr_irqs)
|
||||
{
|
||||
XICSState *icp = NULL;
|
||||
|
||||
icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs);
|
||||
if (!icp) {
|
||||
perror("Failed to create XICS\n");
|
||||
abort();
|
||||
}
|
||||
|
||||
return icp;
|
||||
}
|
||||
|
||||
static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr)
|
||||
{
|
||||
int ret = 0, offset;
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@
|
|||
struct VIOsPAPRBus;
|
||||
struct sPAPRPHBState;
|
||||
struct sPAPRNVRAM;
|
||||
struct icp_state;
|
||||
|
||||
#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
|
||||
|
||||
|
|
@ -15,7 +14,7 @@ typedef struct sPAPREnvironment {
|
|||
struct VIOsPAPRBus *vio_bus;
|
||||
QLIST_HEAD(, sPAPRPHBState) phbs;
|
||||
struct sPAPRNVRAM *nvram;
|
||||
struct icp_state *icp;
|
||||
XICSState *icp;
|
||||
|
||||
hwaddr ram_limit;
|
||||
void *htab;
|
||||
|
|
|
|||
|
|
@ -27,15 +27,77 @@
|
|||
#if !defined(__XICS_H__)
|
||||
#define __XICS_H__
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
|
||||
#define TYPE_XICS "xics"
|
||||
#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
|
||||
|
||||
#define XICS_IPI 0x2
|
||||
#define XICS_IRQ_BASE 0x10
|
||||
#define XICS_BUID 0x1
|
||||
#define XICS_IRQ_BASE (XICS_BUID << 12)
|
||||
|
||||
struct icp_state;
|
||||
/*
|
||||
* We currently only support one BUID which is our interrupt base
|
||||
* (the kernel implementation supports more but we don't exploit
|
||||
* that yet)
|
||||
*/
|
||||
typedef struct XICSState XICSState;
|
||||
typedef struct ICPState ICPState;
|
||||
typedef struct ICSState ICSState;
|
||||
typedef struct ICSIRQState ICSIRQState;
|
||||
|
||||
qemu_irq xics_get_qirq(struct icp_state *icp, int irq);
|
||||
void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi);
|
||||
struct XICSState {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
uint32_t nr_servers;
|
||||
uint32_t nr_irqs;
|
||||
ICPState *ss;
|
||||
ICSState *ics;
|
||||
};
|
||||
|
||||
struct icp_state *xics_system_init(int nr_servers, int nr_irqs);
|
||||
void xics_cpu_setup(struct icp_state *icp, PowerPCCPU *cpu);
|
||||
#define TYPE_ICP "icp"
|
||||
#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
|
||||
|
||||
struct ICPState {
|
||||
/*< private >*/
|
||||
DeviceState parent_obj;
|
||||
/*< public >*/
|
||||
uint32_t xirr;
|
||||
uint8_t pending_priority;
|
||||
uint8_t mfrr;
|
||||
qemu_irq output;
|
||||
};
|
||||
|
||||
#define TYPE_ICS "ics"
|
||||
#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
|
||||
|
||||
struct ICSState {
|
||||
/*< private >*/
|
||||
DeviceState parent_obj;
|
||||
/*< public >*/
|
||||
uint32_t nr_irqs;
|
||||
uint32_t offset;
|
||||
qemu_irq *qirqs;
|
||||
bool *islsi;
|
||||
ICSIRQState *irqs;
|
||||
XICSState *icp;
|
||||
};
|
||||
|
||||
struct ICSIRQState {
|
||||
uint32_t server;
|
||||
uint8_t priority;
|
||||
uint8_t saved_priority;
|
||||
#define XICS_STATUS_ASSERTED 0x1
|
||||
#define XICS_STATUS_SENT 0x2
|
||||
#define XICS_STATUS_REJECTED 0x4
|
||||
#define XICS_STATUS_MASKED_PENDING 0x8
|
||||
uint8_t status;
|
||||
};
|
||||
|
||||
qemu_irq xics_get_qirq(XICSState *icp, int irq);
|
||||
void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
|
||||
|
||||
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
|
||||
|
||||
#endif /* __XICS_H__ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue