ppc patch queue 2021-01-19
Next pull request for qemu-6.0. Not a huge amount here, but it does have some important fixes from Greg Kurz. Includes: * A number of minor cleanups from Daniel Barboza (preliminaries for some hotplug changes that are still under review) * Improved handling of memory hotplug from Greg Kurz * A number of fixes for sam460ex and other 440 based platforms from Zolan Balaton * Some fixes for the QOMification of the PPC 4xx UIC interrupt controller from Peter Maydell -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAmAGerUACgkQbDjKyiDZ s5LjYQ/+M3OYOrvy8thPINm+s5oeJbeCVlavLK9KY4STGzow9HgI0Kl0BkfviK5y X5kLdIWTXTW6SmNUa1Y45kEc2L5wxbXERHGk5WkfoMte0DycOFsWmwdmtAfGKQEI R31+Aj5U/tI+JgtvzlFpHyAqXPzzpLUmnHi9PesD70yU/30FdtI1ZNOA3fRYhN9b iyBubp340Hy4dWSofGYe4L8ieznmNsIDFVsrcj4jzyp0bSNMPPWgqkHAKHmRST6Q wcCQCA8hh5T93JPov/W1q0WB+zB0/LGoNLnqh87sH54CL2QwarYJSKMXjl4nsSfY IRkUO/PW+a+52JHhaACO2aq/qzsNOD/j+8/RE4KBds7wG2XYCY9j3hH0NtcAkHdz M2odtjHYAW3wFBaaoqff76N/MxDd9WJxc222uBunoJLYumRk3XF1e83cwGRsDpTH Vu3O6o4/JhBoon0U52+xTFzdRq5rxwaFdwD+YRTTxycgs6v3tENDnTh+USOQezEq F2W+ESez/7L+HDxUfXs3Lp+RGRyE9aNgeJMfhIyoBY+8n0APZCNz+CwPuqQMxCqi IVb2FMj9duuXfFNt4ubpmtb0nW9wSikWhxQCvhQKxiYfCesv6mvNEXwcqPtt/Ph5 MR1pT45GykYoDrVrZ4sUfxxOGSrFHoxmslZDRSaSXVBWIzF6JIw= =pkwx -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.0-20210119' into staging ppc patch queue 2021-01-19 Next pull request for qemu-6.0. Not a huge amount here, but it does have some important fixes from Greg Kurz. Includes: * A number of minor cleanups from Daniel Barboza (preliminaries for some hotplug changes that are still under review) * Improved handling of memory hotplug from Greg Kurz * A number of fixes for sam460ex and other 440 based platforms from Zolan Balaton * Some fixes for the QOMification of the PPC 4xx UIC interrupt controller from Peter Maydell # gpg: Signature made Tue 19 Jan 2021 06:22:45 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dg-gitlab/tags/ppc-for-6.0-20210119: spapr_cpu_core.c: use g_auto* in spapr_create_vcpu() spapr_rtas.c: fix identation of rtas_ibm_suspend_me() args spapr_hcall.c: make do_client_architecture_support static spapr.h: fix trailing whitespace in phb_placement spapr: Improve handling of memory unplug with old guests sam460ex: Use type cast macro instead of simple cast Revert "ppc4xx: Move common dependency on serial to common option" Revert "sam460ex: Remove FDT_PPC dependency from KConfig" hw/ppc: Remove unused ppcuic_init() hw/ppc/ppc405_uc: Drop use of ppcuic_init() hw/intc/ppc-uic: Make default dcr-base 0xc0, not 0x30 hw/ppc: Delete unused ppc405cr_init() code hw/ppc/sam460ex: Drop use of ppcuic_init() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
c114af1639
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@ -274,7 +274,7 @@ static void ppc_uic_realize(DeviceState *dev, Error **errp)
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static Property ppc_uic_properties[] = {
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DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *),
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DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30),
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DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0),
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DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true),
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DEFINE_PROP_END_OF_LIST()
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};
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@ -36,6 +36,7 @@ config PPC405
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select M48T59
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select PFLASH_CFI02
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select PPC4XX
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select SERIAL
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config PPC440
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bool
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@ -44,6 +45,7 @@ config PPC440
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imply E1000_PCI
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select PCI_EXPRESS
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select PPC4XX
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select SERIAL
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select FDT_PPC
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config PPC4XX
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@ -51,7 +53,6 @@ config PPC4XX
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select BITBANG_I2C
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select PCI
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select PPC_UIC
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select SERIAL
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config SAM460EX
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bool
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@ -60,10 +61,12 @@ config SAM460EX
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select IDE_SII3112
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select M41T80
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select PPC440
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select SERIAL
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select SM501
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select SMBUS_EEPROM
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select USB_EHCI_SYSBUS
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select USB_OHCI
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select FDT_PPC
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config PREP
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bool
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@ -120,6 +123,7 @@ config VIRTEX
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bool
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select PPC4XX
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select PFLASH_CFI01
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select SERIAL
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select XILINX
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select XILINX_ETHLITE
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select FDT_PPC
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@ -62,17 +62,11 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
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void ppc4xx_plb_init(CPUPPCState *env);
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void ppc405_ebc_init(CPUPPCState *env);
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CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
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MemoryRegion ram_memories[4],
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hwaddr ram_bases[4],
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hwaddr ram_sizes[4],
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uint32_t sysclk, qemu_irq **picp,
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int do_init);
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CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
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MemoryRegion ram_memories[2],
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hwaddr ram_bases[2],
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hwaddr ram_sizes[2],
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uint32_t sysclk, qemu_irq **picp,
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uint32_t sysclk, DeviceState **uicdev,
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int do_init);
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#endif /* PPC405_H */
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@ -151,7 +151,6 @@ static void ref405ep_init(MachineState *machine)
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CPUPPCState *env;
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DeviceState *dev;
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SysBusDevice *s;
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qemu_irq *pic;
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MemoryRegion *bios;
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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ram_addr_t bdloc;
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@ -167,6 +166,7 @@ static void ref405ep_init(MachineState *machine)
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int len;
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DriveInfo *dinfo;
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MemoryRegion *sysmem = get_system_memory();
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DeviceState *uicdev;
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if (machine->ram_size != mc->default_ram_size) {
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char *sz = size_to_str(mc->default_ram_size);
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@ -184,7 +184,7 @@ static void ref405ep_init(MachineState *machine)
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ram_bases[1] = 0x00000000;
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ram_sizes[1] = 0x00000000;
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env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
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33333333, &pic, kernel_filename == NULL ? 0 : 1);
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33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
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/* allocate SRAM */
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sram_size = 512 * KiB;
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memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
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@ -429,7 +429,6 @@ static void taihu_405ep_init(MachineState *machine)
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const char *kernel_filename = machine->kernel_filename;
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const char *initrd_filename = machine->initrd_filename;
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char *filename;
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qemu_irq *pic;
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MemoryRegion *sysmem = get_system_memory();
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MemoryRegion *bios;
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MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
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@ -440,6 +439,7 @@ static void taihu_405ep_init(MachineState *machine)
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int linux_boot;
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int fl_idx;
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DriveInfo *dinfo;
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DeviceState *uicdev;
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if (machine->ram_size != mc->default_ram_size) {
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char *sz = size_to_str(mc->default_ram_size);
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@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine)
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"taihu_405ep.ram-1", machine->ram, ram_bases[1],
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ram_sizes[1]);
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ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
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33333333, &pic, kernel_filename == NULL ? 0 : 1);
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33333333, &uicdev, kernel_filename == NULL ? 0 : 1);
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/* allocate and load BIOS */
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fl_idx = 0;
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#if defined(USE_FLASH_BIOS)
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@ -36,6 +36,9 @@
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h"
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#include "hw/intc/ppc-uic.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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//#define DEBUG_OPBA
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//#define DEBUG_SDRAM
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@ -1155,351 +1158,6 @@ static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
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qemu_register_reset(ppc4xx_gpt_reset, gpt);
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}
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/*****************************************************************************/
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/* PowerPC 405CR */
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enum {
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PPC405CR_CPC0_PLLMR = 0x0B0,
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PPC405CR_CPC0_CR0 = 0x0B1,
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PPC405CR_CPC0_CR1 = 0x0B2,
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PPC405CR_CPC0_PSR = 0x0B4,
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PPC405CR_CPC0_JTAGID = 0x0B5,
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PPC405CR_CPC0_ER = 0x0B9,
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PPC405CR_CPC0_FR = 0x0BA,
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PPC405CR_CPC0_SR = 0x0BB,
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};
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enum {
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PPC405CR_CPU_CLK = 0,
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PPC405CR_TMR_CLK = 1,
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PPC405CR_PLB_CLK = 2,
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PPC405CR_SDRAM_CLK = 3,
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PPC405CR_OPB_CLK = 4,
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PPC405CR_EXT_CLK = 5,
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PPC405CR_UART_CLK = 6,
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PPC405CR_CLK_NB = 7,
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};
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typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
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struct ppc405cr_cpc_t {
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clk_setup_t clk_setup[PPC405CR_CLK_NB];
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uint32_t sysclk;
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uint32_t psr;
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uint32_t cr0;
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uint32_t cr1;
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uint32_t jtagid;
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uint32_t pllmr;
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uint32_t er;
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uint32_t fr;
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};
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static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
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{
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uint64_t VCO_out, PLL_out;
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uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
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int M, D0, D1, D2;
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D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
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if (cpc->pllmr & 0x80000000) {
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D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
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D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
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M = D0 * D1 * D2;
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VCO_out = (uint64_t)cpc->sysclk * M;
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if (VCO_out < 400000000 || VCO_out > 800000000) {
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/* PLL cannot lock */
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cpc->pllmr &= ~0x80000000;
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goto bypass_pll;
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}
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PLL_out = VCO_out / D2;
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} else {
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/* Bypass PLL */
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bypass_pll:
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M = D0;
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PLL_out = (uint64_t)cpc->sysclk * M;
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}
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CPU_clk = PLL_out;
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if (cpc->cr1 & 0x00800000)
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TMR_clk = cpc->sysclk; /* Should have a separate clock */
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else
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TMR_clk = CPU_clk;
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PLB_clk = CPU_clk / D0;
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SDRAM_clk = PLB_clk;
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D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
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OPB_clk = PLB_clk / D0;
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D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
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EXT_clk = PLB_clk / D0;
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D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
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UART_clk = CPU_clk / D0;
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/* Setup CPU clocks */
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clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
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/* Setup time-base clock */
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clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
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/* Setup PLB clock */
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clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
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/* Setup SDRAM clock */
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clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
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/* Setup OPB clock */
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clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
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/* Setup external clock */
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clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
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/* Setup UART clock */
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clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
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}
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static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
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{
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ppc405cr_cpc_t *cpc;
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uint32_t ret;
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cpc = opaque;
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switch (dcrn) {
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case PPC405CR_CPC0_PLLMR:
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ret = cpc->pllmr;
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break;
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case PPC405CR_CPC0_CR0:
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ret = cpc->cr0;
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break;
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case PPC405CR_CPC0_CR1:
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ret = cpc->cr1;
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break;
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case PPC405CR_CPC0_PSR:
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ret = cpc->psr;
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break;
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case PPC405CR_CPC0_JTAGID:
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ret = cpc->jtagid;
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break;
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case PPC405CR_CPC0_ER:
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ret = cpc->er;
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break;
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case PPC405CR_CPC0_FR:
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ret = cpc->fr;
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break;
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case PPC405CR_CPC0_SR:
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ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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}
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return ret;
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}
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|
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static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
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{
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ppc405cr_cpc_t *cpc;
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|
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cpc = opaque;
|
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switch (dcrn) {
|
||||
case PPC405CR_CPC0_PLLMR:
|
||||
cpc->pllmr = val & 0xFFF77C3F;
|
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break;
|
||||
case PPC405CR_CPC0_CR0:
|
||||
cpc->cr0 = val & 0x0FFFFFFE;
|
||||
break;
|
||||
case PPC405CR_CPC0_CR1:
|
||||
cpc->cr1 = val & 0x00800000;
|
||||
break;
|
||||
case PPC405CR_CPC0_PSR:
|
||||
/* Read-only */
|
||||
break;
|
||||
case PPC405CR_CPC0_JTAGID:
|
||||
/* Read-only */
|
||||
break;
|
||||
case PPC405CR_CPC0_ER:
|
||||
cpc->er = val & 0xBFFC0000;
|
||||
break;
|
||||
case PPC405CR_CPC0_FR:
|
||||
cpc->fr = val & 0xBFFC0000;
|
||||
break;
|
||||
case PPC405CR_CPC0_SR:
|
||||
/* Read-only */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void ppc405cr_cpc_reset (void *opaque)
|
||||
{
|
||||
ppc405cr_cpc_t *cpc;
|
||||
int D;
|
||||
|
||||
cpc = opaque;
|
||||
/* Compute PLLMR value from PSR settings */
|
||||
cpc->pllmr = 0x80000000;
|
||||
/* PFWD */
|
||||
switch ((cpc->psr >> 30) & 3) {
|
||||
case 0:
|
||||
/* Bypass */
|
||||
cpc->pllmr &= ~0x80000000;
|
||||
break;
|
||||
case 1:
|
||||
/* Divide by 3 */
|
||||
cpc->pllmr |= 5 << 16;
|
||||
break;
|
||||
case 2:
|
||||
/* Divide by 4 */
|
||||
cpc->pllmr |= 4 << 16;
|
||||
break;
|
||||
case 3:
|
||||
/* Divide by 6 */
|
||||
cpc->pllmr |= 2 << 16;
|
||||
break;
|
||||
}
|
||||
/* PFBD */
|
||||
D = (cpc->psr >> 28) & 3;
|
||||
cpc->pllmr |= (D + 1) << 20;
|
||||
/* PT */
|
||||
D = (cpc->psr >> 25) & 7;
|
||||
switch (D) {
|
||||
case 0x2:
|
||||
cpc->pllmr |= 0x13;
|
||||
break;
|
||||
case 0x4:
|
||||
cpc->pllmr |= 0x15;
|
||||
break;
|
||||
case 0x5:
|
||||
cpc->pllmr |= 0x16;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* PDC */
|
||||
D = (cpc->psr >> 23) & 3;
|
||||
cpc->pllmr |= D << 26;
|
||||
/* ODP */
|
||||
D = (cpc->psr >> 21) & 3;
|
||||
cpc->pllmr |= D << 10;
|
||||
/* EBPD */
|
||||
D = (cpc->psr >> 17) & 3;
|
||||
cpc->pllmr |= D << 24;
|
||||
cpc->cr0 = 0x0000003C;
|
||||
cpc->cr1 = 0x2B0D8800;
|
||||
cpc->er = 0x00000000;
|
||||
cpc->fr = 0x00000000;
|
||||
ppc405cr_clk_setup(cpc);
|
||||
}
|
||||
|
||||
static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
|
||||
{
|
||||
int D;
|
||||
|
||||
/* XXX: this should be read from IO pins */
|
||||
cpc->psr = 0x00000000; /* 8 bits ROM */
|
||||
/* PFWD */
|
||||
D = 0x2; /* Divide by 4 */
|
||||
cpc->psr |= D << 30;
|
||||
/* PFBD */
|
||||
D = 0x1; /* Divide by 2 */
|
||||
cpc->psr |= D << 28;
|
||||
/* PDC */
|
||||
D = 0x1; /* Divide by 2 */
|
||||
cpc->psr |= D << 23;
|
||||
/* PT */
|
||||
D = 0x5; /* M = 16 */
|
||||
cpc->psr |= D << 25;
|
||||
/* ODP */
|
||||
D = 0x1; /* Divide by 2 */
|
||||
cpc->psr |= D << 21;
|
||||
/* EBDP */
|
||||
D = 0x2; /* Divide by 4 */
|
||||
cpc->psr |= D << 17;
|
||||
}
|
||||
|
||||
static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
|
||||
uint32_t sysclk)
|
||||
{
|
||||
ppc405cr_cpc_t *cpc;
|
||||
|
||||
cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
|
||||
memcpy(cpc->clk_setup, clk_setup,
|
||||
PPC405CR_CLK_NB * sizeof(clk_setup_t));
|
||||
cpc->sysclk = sysclk;
|
||||
cpc->jtagid = 0x42051049;
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
|
||||
&dcr_read_crcpc, &dcr_write_crcpc);
|
||||
ppc405cr_clk_init(cpc);
|
||||
qemu_register_reset(ppc405cr_cpc_reset, cpc);
|
||||
}
|
||||
|
||||
CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
|
||||
MemoryRegion ram_memories[4],
|
||||
hwaddr ram_bases[4],
|
||||
hwaddr ram_sizes[4],
|
||||
uint32_t sysclk, qemu_irq **picp,
|
||||
int do_init)
|
||||
{
|
||||
clk_setup_t clk_setup[PPC405CR_CLK_NB];
|
||||
qemu_irq dma_irqs[4];
|
||||
PowerPCCPU *cpu;
|
||||
CPUPPCState *env;
|
||||
qemu_irq *pic, *irqs;
|
||||
|
||||
memset(clk_setup, 0, sizeof(clk_setup));
|
||||
cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405crc"),
|
||||
&clk_setup[PPC405CR_CPU_CLK],
|
||||
&clk_setup[PPC405CR_TMR_CLK], sysclk);
|
||||
env = &cpu->env;
|
||||
/* Memory mapped devices registers */
|
||||
/* PLB arbitrer */
|
||||
ppc4xx_plb_init(env);
|
||||
/* PLB to OPB bridge */
|
||||
ppc4xx_pob_init(env);
|
||||
/* OBP arbitrer */
|
||||
ppc4xx_opba_init(0xef600600);
|
||||
/* Universal interrupt controller */
|
||||
irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
|
||||
irqs[PPCUIC_OUTPUT_INT] =
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
||||
irqs[PPCUIC_OUTPUT_CINT] =
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
||||
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
|
||||
*picp = pic;
|
||||
/* SDRAM controller */
|
||||
ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
|
||||
ram_bases, ram_sizes, do_init);
|
||||
/* External bus controller */
|
||||
ppc405_ebc_init(env);
|
||||
/* DMA controller */
|
||||
dma_irqs[0] = pic[26];
|
||||
dma_irqs[1] = pic[25];
|
||||
dma_irqs[2] = pic[24];
|
||||
dma_irqs[3] = pic[23];
|
||||
ppc405_dma_init(env, dma_irqs);
|
||||
/* Serial ports */
|
||||
if (serial_hd(0) != NULL) {
|
||||
serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
if (serial_hd(1) != NULL) {
|
||||
serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
/* IIC controller */
|
||||
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
|
||||
/* GPIO */
|
||||
ppc405_gpio_init(0xef600700);
|
||||
/* CPU control */
|
||||
ppc405cr_cpc_init(env, clk_setup, sysclk);
|
||||
|
||||
return env;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/* PowerPC 405EP */
|
||||
/* CPU control */
|
||||
|
@ -1791,14 +1449,15 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
|
|||
MemoryRegion ram_memories[2],
|
||||
hwaddr ram_bases[2],
|
||||
hwaddr ram_sizes[2],
|
||||
uint32_t sysclk, qemu_irq **picp,
|
||||
uint32_t sysclk, DeviceState **uicdevp,
|
||||
int do_init)
|
||||
{
|
||||
clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
|
||||
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
|
||||
PowerPCCPU *cpu;
|
||||
CPUPPCState *env;
|
||||
qemu_irq *pic, *irqs;
|
||||
DeviceState *uicdev;
|
||||
SysBusDevice *uicsbd;
|
||||
|
||||
memset(clk_setup, 0, sizeof(clk_setup));
|
||||
/* init CPUs */
|
||||
|
@ -1819,59 +1478,69 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
|
|||
/* Initialize timers */
|
||||
ppc_booke_timers_init(cpu, sysclk, 0);
|
||||
/* Universal interrupt controller */
|
||||
irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
|
||||
irqs[PPCUIC_OUTPUT_INT] =
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
||||
irqs[PPCUIC_OUTPUT_CINT] =
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
||||
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
|
||||
*picp = pic;
|
||||
uicdev = qdev_new(TYPE_PPC_UIC);
|
||||
uicsbd = SYS_BUS_DEVICE(uicdev);
|
||||
|
||||
object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
|
||||
&error_fatal);
|
||||
sysbus_realize_and_unref(uicsbd, &error_fatal);
|
||||
|
||||
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
|
||||
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
|
||||
|
||||
*uicdevp = uicdev;
|
||||
|
||||
/* SDRAM controller */
|
||||
/* XXX 405EP has no ECC interrupt */
|
||||
ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
|
||||
ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories,
|
||||
ram_bases, ram_sizes, do_init);
|
||||
/* External bus controller */
|
||||
ppc405_ebc_init(env);
|
||||
/* DMA controller */
|
||||
dma_irqs[0] = pic[5];
|
||||
dma_irqs[1] = pic[6];
|
||||
dma_irqs[2] = pic[7];
|
||||
dma_irqs[3] = pic[8];
|
||||
dma_irqs[0] = qdev_get_gpio_in(uicdev, 5);
|
||||
dma_irqs[1] = qdev_get_gpio_in(uicdev, 6);
|
||||
dma_irqs[2] = qdev_get_gpio_in(uicdev, 7);
|
||||
dma_irqs[3] = qdev_get_gpio_in(uicdev, 8);
|
||||
ppc405_dma_init(env, dma_irqs);
|
||||
/* IIC controller */
|
||||
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]);
|
||||
sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500,
|
||||
qdev_get_gpio_in(uicdev, 2));
|
||||
/* GPIO */
|
||||
ppc405_gpio_init(0xef600700);
|
||||
/* Serial ports */
|
||||
if (serial_hd(0) != NULL) {
|
||||
serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
|
||||
serial_mm_init(address_space_mem, 0xef600300, 0,
|
||||
qdev_get_gpio_in(uicdev, 0),
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
if (serial_hd(1) != NULL) {
|
||||
serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
|
||||
serial_mm_init(address_space_mem, 0xef600400, 0,
|
||||
qdev_get_gpio_in(uicdev, 1),
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
/* OCM */
|
||||
ppc405_ocm_init(env);
|
||||
/* GPT */
|
||||
gpt_irqs[0] = pic[19];
|
||||
gpt_irqs[1] = pic[20];
|
||||
gpt_irqs[2] = pic[21];
|
||||
gpt_irqs[3] = pic[22];
|
||||
gpt_irqs[4] = pic[23];
|
||||
gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19);
|
||||
gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20);
|
||||
gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21);
|
||||
gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22);
|
||||
gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23);
|
||||
ppc4xx_gpt_init(0xef600000, gpt_irqs);
|
||||
/* PCI */
|
||||
/* Uses pic[3], pic[16], pic[18] */
|
||||
/* Uses UIC IRQs 3, 16, 18 */
|
||||
/* MAL */
|
||||
mal_irqs[0] = pic[11];
|
||||
mal_irqs[1] = pic[12];
|
||||
mal_irqs[2] = pic[13];
|
||||
mal_irqs[3] = pic[14];
|
||||
mal_irqs[0] = qdev_get_gpio_in(uicdev, 11);
|
||||
mal_irqs[1] = qdev_get_gpio_in(uicdev, 12);
|
||||
mal_irqs[2] = qdev_get_gpio_in(uicdev, 13);
|
||||
mal_irqs[3] = qdev_get_gpio_in(uicdev, 14);
|
||||
ppc4xx_mal_init(env, 4, 2, mal_irqs);
|
||||
/* Ethernet */
|
||||
/* Uses pic[9], pic[15], pic[17] */
|
||||
/* Uses UIC IRQs 9, 15, 17 */
|
||||
/* CPU control */
|
||||
ppc405ep_cpc_init(env, clk_setup, sysclk);
|
||||
|
||||
|
|
|
@ -77,44 +77,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_type,
|
|||
return cpu;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/* "Universal" Interrupt controller */
|
||||
|
||||
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
|
||||
uint32_t dcr_base, int has_ssr, int has_vr)
|
||||
{
|
||||
DeviceState *uicdev = qdev_new(TYPE_PPC_UIC);
|
||||
SysBusDevice *uicsbd = SYS_BUS_DEVICE(uicdev);
|
||||
qemu_irq *uic_irqs;
|
||||
int i;
|
||||
|
||||
qdev_prop_set_uint32(uicdev, "dcr-base", dcr_base);
|
||||
qdev_prop_set_bit(uicdev, "use-vectors", has_vr);
|
||||
object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(env_cpu(env)),
|
||||
&error_fatal);
|
||||
sysbus_realize_and_unref(uicsbd, &error_fatal);
|
||||
|
||||
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, irqs[PPCUIC_OUTPUT_INT]);
|
||||
sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, irqs[PPCUIC_OUTPUT_CINT]);
|
||||
|
||||
/*
|
||||
* Return an allocated array of the UIC's input IRQ lines.
|
||||
* This is an ugly temporary API to retain compatibility with
|
||||
* the ppcuic_init() interface from the pre-QOM-conversion UIC.
|
||||
* None of the callers free this array, so it is leaked -- but
|
||||
* so was the array allocated by qemu_allocate_irqs() in the
|
||||
* old code.
|
||||
*
|
||||
* The callers should just instantiate the UIC and wire it up
|
||||
* themselves rather than passing qemu_irq* in and out of this function.
|
||||
*/
|
||||
uic_irqs = g_new0(qemu_irq, UIC_MAX_IRQ);
|
||||
for (i = 0; i < UIC_MAX_IRQ; i++) {
|
||||
uic_irqs[i] = qdev_get_gpio_in(uicdev, i);
|
||||
}
|
||||
return uic_irqs;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/* SDRAM controller */
|
||||
typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include "hw/usb/hcd-ehci.h"
|
||||
#include "hw/ppc/fdt.h"
|
||||
#include "hw/qdev-properties.h"
|
||||
#include "hw/intc/ppc-uic.h"
|
||||
|
||||
#include <libfdt.h>
|
||||
|
||||
|
@ -281,7 +282,9 @@ static void sam460ex_init(MachineState *machine)
|
|||
hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
|
||||
hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
|
||||
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
|
||||
qemu_irq *irqs, *uic[4];
|
||||
DeviceState *uic[4];
|
||||
qemu_irq mal_irqs[4];
|
||||
int i;
|
||||
PCIBus *pci_bus;
|
||||
PowerPCCPU *cpu;
|
||||
CPUPPCState *env;
|
||||
|
@ -312,13 +315,38 @@ static void sam460ex_init(MachineState *machine)
|
|||
ppc4xx_plb_init(env);
|
||||
|
||||
/* interrupt controllers */
|
||||
irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
|
||||
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
|
||||
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
|
||||
uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
|
||||
uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
|
||||
uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
|
||||
uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
|
||||
for (i = 0; i < ARRAY_SIZE(uic); i++) {
|
||||
SysBusDevice *sbd;
|
||||
/*
|
||||
* UICs 1, 2 and 3 are cascaded through UIC 0.
|
||||
* input_ints[n] is the interrupt number on UIC 0 which
|
||||
* the INT output of UIC n is connected to. The CINT output
|
||||
* of UIC n connects to input_ints[n] + 1.
|
||||
* The entry in input_ints[] for UIC 0 is ignored, because UIC 0's
|
||||
* INT and CINT outputs are connected to the CPU.
|
||||
*/
|
||||
const int input_ints[] = { -1, 30, 10, 16 };
|
||||
|
||||
uic[i] = qdev_new(TYPE_PPC_UIC);
|
||||
sbd = SYS_BUS_DEVICE(uic[i]);
|
||||
|
||||
qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
|
||||
object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu),
|
||||
&error_fatal);
|
||||
sysbus_realize_and_unref(sbd, &error_fatal);
|
||||
|
||||
if (i == 0) {
|
||||
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
|
||||
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
|
||||
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
|
||||
} else {
|
||||
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
|
||||
qdev_get_gpio_in(uic[0], input_ints[i]));
|
||||
sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
|
||||
qdev_get_gpio_in(uic[0], input_ints[i] + 1));
|
||||
}
|
||||
}
|
||||
|
||||
/* SDRAM controller */
|
||||
/* put all RAM on first bank because board has one slot
|
||||
|
@ -331,7 +359,8 @@ static void sam460ex_init(MachineState *machine)
|
|||
ram_bases, ram_sizes, 1);
|
||||
|
||||
/* IIC controllers and devices */
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
|
||||
qdev_get_gpio_in(uic[0], 2));
|
||||
i2c = PPC4xx_I2C(dev)->bus;
|
||||
/* SPD EEPROM on RAM module */
|
||||
spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2,
|
||||
|
@ -341,7 +370,8 @@ static void sam460ex_init(MachineState *machine)
|
|||
/* RTC */
|
||||
i2c_slave_create_simple(i2c, "m41t80", 0x68);
|
||||
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800,
|
||||
qdev_get_gpio_in(uic[0], 3));
|
||||
|
||||
/* External bus controller */
|
||||
ppc405_ebc_init(env);
|
||||
|
@ -356,7 +386,10 @@ static void sam460ex_init(MachineState *machine)
|
|||
ppc4xx_sdr_init(env);
|
||||
|
||||
/* MAL */
|
||||
ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
|
||||
for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) {
|
||||
mal_irqs[0] = qdev_get_gpio_in(uic[2], 3 + i);
|
||||
}
|
||||
ppc4xx_mal_init(env, 4, 16, mal_irqs);
|
||||
|
||||
/* DMA */
|
||||
ppc4xx_dma_init(env, 0x200);
|
||||
|
@ -369,26 +402,25 @@ static void sam460ex_init(MachineState *machine)
|
|||
memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
|
||||
|
||||
/* USB */
|
||||
sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
|
||||
sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400,
|
||||
qdev_get_gpio_in(uic[2], 29));
|
||||
dev = qdev_new("sysbus-ohci");
|
||||
qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
|
||||
qdev_prop_set_uint32(dev, "num-ports", 6);
|
||||
sbdev = SYS_BUS_DEVICE(dev);
|
||||
sysbus_realize_and_unref(sbdev, &error_fatal);
|
||||
sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
|
||||
sysbus_connect_irq(sbdev, 0, uic[2][30]);
|
||||
sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30));
|
||||
usb_create_simple(usb_bus_find(-1), "usb-kbd");
|
||||
usb_create_simple(usb_bus_find(-1), "usb-mouse");
|
||||
|
||||
/* PCI bus */
|
||||
ppc460ex_pcie_init(env);
|
||||
/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
|
||||
dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]);
|
||||
pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
|
||||
if (!pci_bus) {
|
||||
error_report("couldn't create PCI controller!");
|
||||
exit(1);
|
||||
}
|
||||
dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000,
|
||||
qdev_get_gpio_in(uic[1], 0));
|
||||
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
|
||||
|
||||
memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
|
||||
0, 0x10000);
|
||||
memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
|
||||
|
@ -405,12 +437,14 @@ static void sam460ex_init(MachineState *machine)
|
|||
/* SoC has 4 UARTs
|
||||
* but board has only one wired and two are present in fdt */
|
||||
if (serial_hd(0) != NULL) {
|
||||
serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
|
||||
serial_mm_init(address_space_mem, 0x4ef600300, 0,
|
||||
qdev_get_gpio_in(uic[1], 1),
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
if (serial_hd(1) != NULL) {
|
||||
serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
|
||||
serial_mm_init(address_space_mem, 0x4ef600400, 0,
|
||||
qdev_get_gpio_in(uic[0], 1),
|
||||
PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
|
||||
DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
|
|
|
@ -4048,6 +4048,18 @@ static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
|
|||
}
|
||||
}
|
||||
|
||||
bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr)
|
||||
{
|
||||
return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) ||
|
||||
/*
|
||||
* CAS will process all pending unplug requests.
|
||||
*
|
||||
* HACK: a guest could theoretically have cleared all bits in OV5,
|
||||
* but none of the guests we care for do.
|
||||
*/
|
||||
spapr_ovec_empty(spapr->ov5_cas);
|
||||
}
|
||||
|
||||
static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
|
||||
DeviceState *dev, Error **errp)
|
||||
{
|
||||
|
@ -4056,16 +4068,9 @@ static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
|
|||
SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
|
||||
|
||||
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
|
||||
if (!smc->pre_6_0_memory_unplug ||
|
||||
spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
|
||||
if (spapr_memory_hot_unplug_supported(sms)) {
|
||||
spapr_memory_unplug_request(hotplug_dev, dev, errp);
|
||||
} else {
|
||||
/* NOTE: this means there is a window after guest reset, prior to
|
||||
* CAS negotiation, where unplug requests will fail due to the
|
||||
* capability not being detected yet. This is a bit different than
|
||||
* the case with PCI unplug, where the events will be queued and
|
||||
* eventually handled by the guest after boot
|
||||
*/
|
||||
error_setg(errp, "Memory hot unplug not supported for this guest");
|
||||
}
|
||||
} else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
|
||||
|
@ -4543,11 +4548,8 @@ DEFINE_SPAPR_MACHINE(6_0, "6.0", true);
|
|||
*/
|
||||
static void spapr_machine_5_2_class_options(MachineClass *mc)
|
||||
{
|
||||
SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
|
||||
|
||||
spapr_machine_6_0_class_options(mc);
|
||||
compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
|
||||
smc->pre_6_0_memory_unplug = true;
|
||||
}
|
||||
|
||||
DEFINE_SPAPR_MACHINE(5_2, "5.2", false);
|
||||
|
|
|
@ -277,8 +277,8 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
|
|||
{
|
||||
SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
|
||||
CPUCore *cc = CPU_CORE(sc);
|
||||
Object *obj;
|
||||
char *id;
|
||||
g_autoptr(Object) obj = NULL;
|
||||
g_autofree char *id = NULL;
|
||||
CPUState *cs;
|
||||
PowerPCCPU *cpu;
|
||||
|
||||
|
@ -293,23 +293,17 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
|
|||
cs->start_powered_off = true;
|
||||
cs->cpu_index = cc->core_id + i;
|
||||
if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
|
||||
goto err;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cpu->node_id = sc->node_id;
|
||||
|
||||
id = g_strdup_printf("thread[%d]", i);
|
||||
object_property_add_child(OBJECT(sc), id, obj);
|
||||
g_free(id);
|
||||
|
||||
cpu->machine_data = g_new0(SpaprCpuState, 1);
|
||||
|
||||
object_unref(obj);
|
||||
return cpu;
|
||||
|
||||
err:
|
||||
object_unref(obj);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
|
||||
|
|
|
@ -658,8 +658,7 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
|
|||
/* we should not be using count_indexed value unless the guest
|
||||
* supports dedicated hotplug event source
|
||||
*/
|
||||
g_assert(!SPAPR_MACHINE_GET_CLASS(spapr)->pre_6_0_memory_unplug ||
|
||||
spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT));
|
||||
g_assert(spapr_memory_hot_unplug_supported(spapr));
|
||||
hp->drc_id.count_indexed.count =
|
||||
cpu_to_be32(drc_id->count_indexed.count);
|
||||
hp->drc_id.count_indexed.index =
|
||||
|
|
|
@ -1632,6 +1632,7 @@ static uint32_t cas_check_pvr(PowerPCCPU *cpu, uint32_t max_compat,
|
|||
return best_compat;
|
||||
}
|
||||
|
||||
static
|
||||
target_ulong do_client_architecture_support(PowerPCCPU *cpu,
|
||||
SpaprMachineState *spapr,
|
||||
target_ulong vec,
|
||||
|
|
|
@ -125,6 +125,13 @@ bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr)
|
|||
return test_bit(bitnr, ov->bitmap) ? true : false;
|
||||
}
|
||||
|
||||
bool spapr_ovec_empty(SpaprOptionVector *ov)
|
||||
{
|
||||
g_assert(ov);
|
||||
|
||||
return bitmap_empty(ov->bitmap, OV_MAXBITS);
|
||||
}
|
||||
|
||||
static void guest_byte_to_bitmap(uint8_t entry, unsigned long *bitmap,
|
||||
long bitmap_offset)
|
||||
{
|
||||
|
|
|
@ -219,9 +219,9 @@ static void rtas_stop_self(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
|||
}
|
||||
|
||||
static void rtas_ibm_suspend_me(PowerPCCPU *cpu, SpaprMachineState *spapr,
|
||||
uint32_t token, uint32_t nargs,
|
||||
target_ulong args,
|
||||
uint32_t nret, target_ulong rets)
|
||||
uint32_t token, uint32_t nargs,
|
||||
target_ulong args,
|
||||
uint32_t nret, target_ulong rets)
|
||||
{
|
||||
CPUState *cs;
|
||||
|
||||
|
|
|
@ -47,6 +47,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(PPCUIC, PPC_UIC)
|
|||
|
||||
#define UIC_MAX_IRQ 32
|
||||
|
||||
/* Symbolic constants for the sysbus IRQ outputs */
|
||||
enum {
|
||||
PPCUIC_OUTPUT_INT = 0,
|
||||
PPCUIC_OUTPUT_CINT = 1,
|
||||
PPCUIC_OUTPUT_NB,
|
||||
};
|
||||
|
||||
struct PPCUIC {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
|
|
@ -33,15 +33,6 @@ PowerPCCPU *ppc4xx_init(const char *cpu_model,
|
|||
clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
|
||||
uint32_t sysclk);
|
||||
|
||||
/* PowerPC 4xx universal interrupt controller */
|
||||
enum {
|
||||
PPCUIC_OUTPUT_INT = 0,
|
||||
PPCUIC_OUTPUT_CINT = 1,
|
||||
PPCUIC_OUTPUT_NB,
|
||||
};
|
||||
qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
|
||||
uint32_t dcr_base, int has_ssr, int has_vr);
|
||||
|
||||
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
|
||||
MemoryRegion ram_memories[],
|
||||
hwaddr ram_bases[], hwaddr ram_sizes[],
|
||||
|
|
|
@ -142,7 +142,6 @@ struct SpaprMachineClass {
|
|||
hwaddr rma_limit; /* clamp the RMA to this size */
|
||||
bool pre_5_1_assoc_refpoints;
|
||||
bool pre_5_2_numa_associativity;
|
||||
bool pre_6_0_memory_unplug;
|
||||
|
||||
bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
|
||||
uint64_t *buid, hwaddr *pio,
|
||||
|
@ -583,11 +582,6 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
|
|||
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
|
||||
target_ulong *args);
|
||||
|
||||
target_ulong do_client_architecture_support(PowerPCCPU *cpu,
|
||||
SpaprMachineState *spapr,
|
||||
target_ulong addr,
|
||||
target_ulong fdt_bufsize);
|
||||
|
||||
/* Virtual Processor Area structure constants */
|
||||
#define VPA_MIN_SIZE 640
|
||||
#define VPA_SIZE_OFFSET 0x4
|
||||
|
@ -950,4 +944,5 @@ bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
|
|||
|
||||
void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
|
||||
hwaddr spapr_get_rtas_addr(void);
|
||||
bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr);
|
||||
#endif /* HW_SPAPR_H */
|
||||
|
|
|
@ -71,6 +71,7 @@ void spapr_ovec_cleanup(SpaprOptionVector *ov);
|
|||
void spapr_ovec_set(SpaprOptionVector *ov, long bitnr);
|
||||
void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr);
|
||||
bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr);
|
||||
bool spapr_ovec_empty(SpaprOptionVector *ov);
|
||||
SpaprOptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector);
|
||||
int spapr_dt_ovec(void *fdt, int fdt_offset,
|
||||
SpaprOptionVector *ov, const char *name);
|
||||
|
|
Loading…
Reference in a new issue