target/arm: Share table of sve load functions
The table used by do_ldrq is a subset of the table used by do_ld_zpa; we can share them by passing dtype instead of msz to do_ldrq. The lack of MTE handling in do_ldrq was a bug, fixed by this change. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-77-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -5215,10 +5215,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
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tcg_temp_free_i32(t_desc);
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}
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static void do_ld_zpa(DisasContext *s, int zt, int pg,
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TCGv_i64 addr, int dtype, int nreg)
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{
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static gen_helper_gvec_mem * const fns[2][2][16][4] = {
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/* Indexed by [mte][be][dtype][nreg] */
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static gen_helper_gvec_mem * const ldr_fns[2][2][16][4] = {
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{ /* mte inactive, little-endian */
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{ { gen_helper_sve_ld1bb_r, gen_helper_sve_ld2bb_r,
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gen_helper_sve_ld3bb_r, gen_helper_sve_ld4bb_r },
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@ -5335,8 +5333,12 @@ static void do_ld_zpa(DisasContext *s, int zt, int pg,
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gen_helper_sve_ld3dd_be_r_mte,
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gen_helper_sve_ld4dd_be_r_mte } } },
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};
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static void do_ld_zpa(DisasContext *s, int zt, int pg,
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TCGv_i64 addr, int dtype, int nreg)
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{
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gen_helper_gvec_mem *fn
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= fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg];
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= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][nreg];
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/*
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* While there are holes in the table, they are not
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@ -5574,14 +5576,8 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
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return true;
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}
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static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
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static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype)
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{
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static gen_helper_gvec_mem * const fns[2][4] = {
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{ gen_helper_sve_ld1bb_r, gen_helper_sve_ld1hh_le_r,
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gen_helper_sve_ld1ss_le_r, gen_helper_sve_ld1dd_le_r },
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{ gen_helper_sve_ld1bb_r, gen_helper_sve_ld1hh_be_r,
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gen_helper_sve_ld1ss_be_r, gen_helper_sve_ld1dd_be_r },
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};
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unsigned vsz = vec_full_reg_size(s);
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TCGv_ptr t_pg;
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TCGv_i32 t_desc;
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@ -5613,7 +5609,9 @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz)
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t_pg = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(t_pg, cpu_env, poff);
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fns[s->be_data == MO_BE][msz](cpu_env, t_pg, addr, t_desc);
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gen_helper_gvec_mem *fn
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= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
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fn(cpu_env, t_pg, addr, t_desc);
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tcg_temp_free_ptr(t_pg);
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tcg_temp_free_i32(t_desc);
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@ -5635,7 +5633,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a)
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TCGv_i64 addr = new_tmp_a64(s);
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tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz);
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tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
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do_ldrq(s, a->rd, a->pg, addr, msz);
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do_ldrq(s, a->rd, a->pg, addr, a->dtype);
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}
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return true;
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}
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@ -5645,7 +5643,7 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a)
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if (sve_access_check(s)) {
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TCGv_i64 addr = new_tmp_a64(s);
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tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16);
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do_ldrq(s, a->rd, a->pg, addr, dtype_msz(a->dtype));
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do_ldrq(s, a->rd, a->pg, addr, a->dtype);
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}
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return true;
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}
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