Allow ISA to be disabled on some platforms (v3)
This makes some cleanups that are a start on allowing ISA to be compiled out for platforms which don't use it. I posted this series last November, and it collected a number of R-bs and no apparent objections. So, I've now rebased it (trivially) and am sending a pull request in the hopes of merge. A lot of the pieces here don't have a clear maintainer, so I'm sending it directly to Peter. Notes: * Patch 3/3 triggers a style warning, but that's just because I'm moving a C++ // comment verbatim from one file to another Changes since v2: * Trivial rebase Changes since v1: * Fixed some silly compile errors in 3/3 exposed by some changes in other headers -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJYl9NuAAoJEGw4ysog2bOScQ0P/iHg9XVMOCr6E4YLxHN0bagB vLRCYVkUDeucMSZ7ARyIUR/Cp8uQGtTPpukcyscX7/1nim+n/FVWnW4noDeptauk PjtPdOydu3Ml9lFtTGkpEUOrUrViVEWrDH0NScLECSKFdACtokfF30T2iYo1oPuG A6UCurn4zeS75iMsFXK+i871wiQtGFN1B/liE67SJ39K7vqHmNc7lyn/WUXtr0X0 eQwHcFxiPDjR/pssAv1naUs6NBnbvb/iHpqUlUAhxeiBJ02DQ9qV2lb/XJaly/NZ SFg++ij4XDWT5aZbee9COmonUjwcKrj0W+vwAbWLOnG/HviGwDkzAGhbLgtfsIPt J/XZDuLUm9GSS+lW7pqmrW7G0R6zh43nxD+jJiFh2V+aqSmIxFoRAAAo8ft0y0QW JdclrCCfJwmYmS27xtpl6J0lQfwP7w/ta5anx6ohBwR8sma9zBz/QqC6jP+QY18h qLsYvVwXhCKMzNUONED5zCTm30j4Lpdcn1xwA544EyeN8NUUzgjUgvzl/wEt7P/l Icnd8uMjCRn9ZCxDdjIOP7QkFFwo/3QoQoOcRspNIEwBHVnuJFBLwFRIa+27txFE GZKqMIzgRVf7QbwR+wZwutJgIJ7xXoviHm2I8k2L0epyB1kiU+mSywg0l/3DmB5q IlhUpHpWEVO2oxwWwm/p =87oO -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/isa-cleanup-20170206' into staging Allow ISA to be disabled on some platforms (v3) This makes some cleanups that are a start on allowing ISA to be compiled out for platforms which don't use it. I posted this series last November, and it collected a number of R-bs and no apparent objections. So, I've now rebased it (trivially) and am sending a pull request in the hopes of merge. A lot of the pieces here don't have a clear maintainer, so I'm sending it directly to Peter. Notes: * Patch 3/3 triggers a style warning, but that's just because I'm moving a C++ // comment verbatim from one file to another Changes since v2: * Trivial rebase Changes since v1: * Fixed some silly compile errors in 3/3 exposed by some changes in other headers # gpg: Signature made Mon 06 Feb 2017 01:37:50 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/isa-cleanup-20170206: Split ISA and sysbus versions of m48t59 device Allow ISA bus to be configured out Split serial-isa into its own config option Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
c192325242
|
@ -3,6 +3,7 @@
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|||
include pci.mak
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include usb.mak
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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||||
CONFIG_I8254=y
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CONFIG_PCKBD=y
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||||
CONFIG_VGA_CIRRUS=y
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||||
|
|
|
@ -6,6 +6,7 @@ CONFIG_VGA=y
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CONFIG_NAND=y
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CONFIG_ECC=y
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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CONFIG_PTIMER=y
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CONFIG_SD=y
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||||
CONFIG_MAX7310=y
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||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_IPMI_EXTERN=y
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CONFIG_ISA_IPMI_KCS=y
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CONFIG_ISA_IPMI_BT=y
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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CONFIG_PARALLEL=y
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CONFIG_I8254=y
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CONFIG_PCSPK=y
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|
|
|
@ -9,6 +9,7 @@ CONFIG_VGA_ISA_MM=y
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CONFIG_VGA_CIRRUS=y
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CONFIG_VMWARE_VGA=y
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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CONFIG_PARALLEL=y
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CONFIG_I8254=y
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CONFIG_PCSPK=y
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|
|
|
@ -1,5 +1,7 @@
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# Default configuration for moxie-softmmu
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|
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CONFIG_ISA_BUS=y
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CONFIG_MC146818RTC=y
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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CONFIG_VGA=y
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|
|
|
@ -1,4 +1,6 @@
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CONFIG_PCI=y
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# For now, CONFIG_IDE_CORE requires ISA, so we enable it here
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CONFIG_ISA_BUS=y
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CONFIG_VIRTIO_PCI=y
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CONFIG_VIRTIO=y
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CONFIG_USB_UHCI=y
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|
@ -27,6 +29,7 @@ CONFIG_AHCI=y
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CONFIG_ESP=y
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CONFIG_ESP_PCI=y
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CONFIG_SERIAL=y
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CONFIG_SERIAL_ISA=y
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CONFIG_SERIAL_PCI=y
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CONFIG_IPACK=y
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CONFIG_WDT_IB6300ESB=y
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|
|
|
@ -46,6 +46,7 @@ CONFIG_PLATFORM_BUS=y
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CONFIG_ETSEC=y
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CONFIG_LIBDECNUMBER=y
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# For PReP
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CONFIG_SERIAL_ISA=y
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CONFIG_MC146818RTC=y
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CONFIG_ISA_TESTDEV=y
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CONFIG_RS6000_MC=y
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|
|
|
@ -52,6 +52,7 @@ CONFIG_XICS=$(CONFIG_PSERIES)
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CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
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CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
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# For PReP
|
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CONFIG_SERIAL_ISA=y
|
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CONFIG_MC146818RTC=y
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CONFIG_ISA_TESTDEV=y
|
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CONFIG_MEM_HOTPLUG=y
|
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|
|
|
@ -5,6 +5,7 @@ include sound.mak
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include usb.mak
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CONFIG_M48T59=y
|
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CONFIG_SERIAL=y
|
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CONFIG_SERIAL_ISA=y
|
||||
CONFIG_I8257=y
|
||||
CONFIG_OPENPIC=y
|
||||
CONFIG_PFLASH_CFI01=y
|
||||
|
|
|
@ -3,6 +3,7 @@
|
|||
include pci.mak
|
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include usb.mak
|
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CONFIG_SERIAL=y
|
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CONFIG_SERIAL_ISA=y
|
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CONFIG_PTIMER=y
|
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CONFIG_PFLASH_CFI02=y
|
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CONFIG_SH4=y
|
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|
|
|
@ -3,6 +3,7 @@
|
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include pci.mak
|
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include usb.mak
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_SERIAL_ISA=y
|
||||
CONFIG_PTIMER=y
|
||||
CONFIG_PFLASH_CFI02=y
|
||||
CONFIG_SH4=y
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
# Default configuration for sparc-softmmu
|
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|
||||
CONFIG_ISA_BUS=y
|
||||
CONFIG_ECC=y
|
||||
CONFIG_ESP=y
|
||||
CONFIG_ESCC=y
|
||||
|
|
|
@ -5,6 +5,7 @@ include usb.mak
|
|||
CONFIG_M48T59=y
|
||||
CONFIG_PTIMER=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_SERIAL_ISA=y
|
||||
CONFIG_PARALLEL=y
|
||||
CONFIG_PCKBD=y
|
||||
CONFIG_FDC=y
|
||||
|
|
|
@ -1,4 +1,5 @@
|
|||
# Default configuration for unicore32-softmmu
|
||||
CONFIG_ISA_BUS=y
|
||||
CONFIG_PUV3=y
|
||||
CONFIG_PTIMER=y
|
||||
CONFIG_PCKBD=y
|
||||
|
|
|
@ -15,6 +15,7 @@ CONFIG_IPMI_EXTERN=y
|
|||
CONFIG_ISA_IPMI_KCS=y
|
||||
CONFIG_ISA_IPMI_BT=y
|
||||
CONFIG_SERIAL=y
|
||||
CONFIG_SERIAL_ISA=y
|
||||
CONFIG_PARALLEL=y
|
||||
CONFIG_I8254=y
|
||||
CONFIG_PCSPK=y
|
||||
|
|
|
@ -2,7 +2,8 @@ common-obj-$(CONFIG_IPACK) += ipoctal232.o
|
|||
common-obj-$(CONFIG_ESCC) += escc.o
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||||
common-obj-$(CONFIG_PARALLEL) += parallel.o
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common-obj-$(CONFIG_PL011) += pl011.o
|
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common-obj-$(CONFIG_SERIAL) += serial.o serial-isa.o
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common-obj-$(CONFIG_SERIAL) += serial.o
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common-obj-$(CONFIG_SERIAL_ISA) += serial-isa.o
|
||||
common-obj-$(CONFIG_SERIAL_PCI) += serial-pci.o
|
||||
common-obj-$(CONFIG_VIRTIO) += virtio-console.o
|
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common-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
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|
|
|
@ -1,4 +1,4 @@
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common-obj-y += isa-bus.o
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common-obj-$(CONFIG_ISA_BUS) += isa-bus.o
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common-obj-$(CONFIG_APM) += apm.o
|
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common-obj-$(CONFIG_I82378) += i82378.o
|
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common-obj-$(CONFIG_PC87312) += pc87312.o
|
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|
|
|
@ -6,6 +6,9 @@ common-obj-$(CONFIG_DS1338) += ds1338.o
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common-obj-$(CONFIG_HPET) += hpet.o
|
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common-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
|
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common-obj-$(CONFIG_M48T59) += m48t59.o
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ifeq ($(CONFIG_ISA_BUS),y)
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common-obj-$(CONFIG_M48T59) += m48t59-isa.o
|
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endif
|
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common-obj-$(CONFIG_PL031) += pl031.o
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common-obj-$(CONFIG_PUV3) += puv3_ost.o
|
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common-obj-$(CONFIG_TWL92230) += twl92230.o
|
||||
|
|
82
hw/timer/m48t59-internal.h
Normal file
82
hw/timer/m48t59-internal.h
Normal file
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* QEMU M48T59 and M48T08 NVRAM emulation (common header)
|
||||
*
|
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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* Copyright (c) 2013 Hervé Poussineau
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
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#ifndef HW_M48T59_INTERNAL_H
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#define HW_M48T59_INTERNAL_H 1
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|
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//#define DEBUG_NVRAM
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|
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#if defined(DEBUG_NVRAM)
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#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
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#else
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#define NVRAM_PRINTF(fmt, ...) do { } while (0)
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#endif
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|
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/*
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* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
|
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* alarm and a watchdog timer and related control registers. In the
|
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* PPC platform there is also a nvram lock function.
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*/
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|
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typedef struct M48txxInfo {
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const char *bus_name;
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uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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uint32_t size;
|
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} M48txxInfo;
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|
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typedef struct M48t59State {
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/* Hardware parameters */
|
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qemu_irq IRQ;
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MemoryRegion iomem;
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uint32_t size;
|
||||
int32_t base_year;
|
||||
/* RTC management */
|
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time_t time_offset;
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time_t stop_time;
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||||
/* Alarm & watchdog */
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struct tm alarm;
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QEMUTimer *alrm_timer;
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QEMUTimer *wd_timer;
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/* NVRAM storage */
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uint8_t *buffer;
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/* Model parameters */
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uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
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/* NVRAM storage */
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uint16_t addr;
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uint8_t lock;
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} M48t59State;
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uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr);
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void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val);
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void m48t59_reset_common(M48t59State *NVRAM);
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void m48t59_realize_common(M48t59State *s, Error **errp);
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|
||||
static inline void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
|
||||
{
|
||||
NVRAM->lock ^= 1 << lock;
|
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}
|
||||
|
||||
extern const MemoryRegionOps m48t59_io_ops;
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|
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#endif /* HW_M48T59_INTERNAL_H */
|
181
hw/timer/m48t59-isa.c
Normal file
181
hw/timer/m48t59-isa.c
Normal file
|
@ -0,0 +1,181 @@
|
|||
/*
|
||||
* QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface
|
||||
*
|
||||
* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
|
||||
* Copyright (c) 2013 Hervé Poussineau
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#include "qemu/osdep.h"
|
||||
#include "hw/isa/isa.h"
|
||||
#include "hw/timer/m48t59.h"
|
||||
#include "m48t59-internal.h"
|
||||
|
||||
#define TYPE_M48TXX_ISA "isa-m48txx"
|
||||
#define M48TXX_ISA_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
|
||||
#define M48TXX_ISA_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
|
||||
#define M48TXX_ISA(obj) \
|
||||
OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
|
||||
|
||||
typedef struct M48txxISAState {
|
||||
ISADevice parent_obj;
|
||||
M48t59State state;
|
||||
uint32_t io_base;
|
||||
MemoryRegion io;
|
||||
} M48txxISAState;
|
||||
|
||||
typedef struct M48txxISADeviceClass {
|
||||
ISADeviceClass parent_class;
|
||||
M48txxInfo info;
|
||||
} M48txxISADeviceClass;
|
||||
|
||||
static M48txxInfo m48txx_isa_info[] = {
|
||||
{
|
||||
.bus_name = "isa-m48t59",
|
||||
.model = 59,
|
||||
.size = 0x2000,
|
||||
}
|
||||
};
|
||||
|
||||
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int base_year, int model)
|
||||
{
|
||||
DeviceState *dev;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
|
||||
if (m48txx_isa_info[i].size != size ||
|
||||
m48txx_isa_info[i].model != model) {
|
||||
continue;
|
||||
}
|
||||
|
||||
dev = DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name));
|
||||
qdev_prop_set_uint32(dev, "iobase", io_base);
|
||||
qdev_prop_set_int32(dev, "base-year", base_year);
|
||||
qdev_init_nofail(dev);
|
||||
return NVRAM(dev);
|
||||
}
|
||||
|
||||
assert(false);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
return m48t59_read(&d->state, addr);
|
||||
}
|
||||
|
||||
static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
m48t59_write(&d->state, addr, val);
|
||||
}
|
||||
|
||||
static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
m48t59_toggle_lock(&d->state, lock);
|
||||
}
|
||||
|
||||
static Property m48t59_isa_properties[] = {
|
||||
DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
|
||||
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void m48t59_reset_isa(DeviceState *d)
|
||||
{
|
||||
M48txxISAState *isa = M48TXX_ISA(d);
|
||||
M48t59State *NVRAM = &isa->state;
|
||||
|
||||
m48t59_reset_common(NVRAM);
|
||||
}
|
||||
|
||||
static void m48t59_isa_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
|
||||
ISADevice *isadev = ISA_DEVICE(dev);
|
||||
M48txxISAState *d = M48TXX_ISA(dev);
|
||||
M48t59State *s = &d->state;
|
||||
|
||||
s->model = u->info.model;
|
||||
s->size = u->info.size;
|
||||
isa_init_irq(isadev, &s->IRQ, 8);
|
||||
m48t59_realize_common(s, errp);
|
||||
memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
|
||||
if (d->io_base != 0) {
|
||||
isa_register_ioport(isadev, &d->io, d->io_base);
|
||||
}
|
||||
}
|
||||
|
||||
static void m48txx_isa_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
NvramClass *nc = NVRAM_CLASS(klass);
|
||||
|
||||
dc->realize = m48t59_isa_realize;
|
||||
dc->reset = m48t59_reset_isa;
|
||||
dc->props = m48t59_isa_properties;
|
||||
nc->read = m48txx_isa_read;
|
||||
nc->write = m48txx_isa_write;
|
||||
nc->toggle_lock = m48txx_isa_toggle_lock;
|
||||
}
|
||||
|
||||
static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
|
||||
M48txxInfo *info = data;
|
||||
|
||||
u->info = *info;
|
||||
}
|
||||
|
||||
static const TypeInfo m48txx_isa_type_info = {
|
||||
.name = TYPE_M48TXX_ISA,
|
||||
.parent = TYPE_ISA_DEVICE,
|
||||
.instance_size = sizeof(M48txxISAState),
|
||||
.abstract = true,
|
||||
.class_init = m48txx_isa_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ TYPE_NVRAM },
|
||||
{ }
|
||||
}
|
||||
};
|
||||
|
||||
static void m48t59_isa_register_types(void)
|
||||
{
|
||||
TypeInfo isa_type_info = {
|
||||
.parent = TYPE_M48TXX_ISA,
|
||||
.class_size = sizeof(M48txxISADeviceClass),
|
||||
.class_init = m48txx_isa_concrete_class_init,
|
||||
};
|
||||
int i;
|
||||
|
||||
type_register_static(&m48txx_isa_type_info);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
|
||||
isa_type_info.name = m48txx_isa_info[i].bus_name;
|
||||
isa_type_info.class_data = &m48txx_isa_info[i];
|
||||
type_register(&isa_type_info);
|
||||
}
|
||||
}
|
||||
|
||||
type_init(m48t59_isa_register_types)
|
|
@ -29,17 +29,10 @@
|
|||
#include "qemu/timer.h"
|
||||
#include "sysemu/sysemu.h"
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/isa/isa.h"
|
||||
#include "exec/address-spaces.h"
|
||||
#include "qemu/bcd.h"
|
||||
|
||||
//#define DEBUG_NVRAM
|
||||
|
||||
#if defined(DEBUG_NVRAM)
|
||||
#define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
|
||||
#else
|
||||
#define NVRAM_PRINTF(fmt, ...) do { } while (0)
|
||||
#endif
|
||||
#include "m48t59-internal.h"
|
||||
|
||||
#define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
|
||||
#define M48TXX_SYS_BUS_GET_CLASS(obj) \
|
||||
|
@ -49,27 +42,6 @@
|
|||
#define M48TXX_SYS_BUS(obj) \
|
||||
OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
|
||||
|
||||
#define TYPE_M48TXX_ISA "isa-m48txx"
|
||||
#define M48TXX_ISA_GET_CLASS(obj) \
|
||||
OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
|
||||
#define M48TXX_ISA_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
|
||||
#define M48TXX_ISA(obj) \
|
||||
OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
|
||||
|
||||
/*
|
||||
* The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
|
||||
* alarm and a watchdog timer and related control registers. In the
|
||||
* PPC platform there is also a nvram lock function.
|
||||
*/
|
||||
|
||||
typedef struct M48txxInfo {
|
||||
const char *isa_name;
|
||||
const char *sysbus_name;
|
||||
uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
|
||||
uint32_t size;
|
||||
} M48txxInfo;
|
||||
|
||||
/*
|
||||
* Chipset docs:
|
||||
* http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
|
||||
|
@ -77,40 +49,6 @@ typedef struct M48txxInfo {
|
|||
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
|
||||
*/
|
||||
|
||||
typedef struct M48t59State {
|
||||
/* Hardware parameters */
|
||||
qemu_irq IRQ;
|
||||
MemoryRegion iomem;
|
||||
uint32_t size;
|
||||
int32_t base_year;
|
||||
/* RTC management */
|
||||
time_t time_offset;
|
||||
time_t stop_time;
|
||||
/* Alarm & watchdog */
|
||||
struct tm alarm;
|
||||
QEMUTimer *alrm_timer;
|
||||
QEMUTimer *wd_timer;
|
||||
/* NVRAM storage */
|
||||
uint8_t *buffer;
|
||||
/* Model parameters */
|
||||
uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
|
||||
/* NVRAM storage */
|
||||
uint16_t addr;
|
||||
uint8_t lock;
|
||||
} M48t59State;
|
||||
|
||||
typedef struct M48txxISAState {
|
||||
ISADevice parent_obj;
|
||||
M48t59State state;
|
||||
uint32_t io_base;
|
||||
MemoryRegion io;
|
||||
} M48txxISAState;
|
||||
|
||||
typedef struct M48txxISADeviceClass {
|
||||
ISADeviceClass parent_class;
|
||||
M48txxInfo info;
|
||||
} M48txxISADeviceClass;
|
||||
|
||||
typedef struct M48txxSysBusState {
|
||||
SysBusDevice parent_obj;
|
||||
M48t59State state;
|
||||
|
@ -122,21 +60,17 @@ typedef struct M48txxSysBusDeviceClass {
|
|||
M48txxInfo info;
|
||||
} M48txxSysBusDeviceClass;
|
||||
|
||||
static M48txxInfo m48txx_info[] = {
|
||||
static M48txxInfo m48txx_sysbus_info[] = {
|
||||
{
|
||||
.sysbus_name = "sysbus-m48t02",
|
||||
.bus_name = "sysbus-m48t02",
|
||||
.model = 2,
|
||||
.size = 0x800,
|
||||
},{
|
||||
.sysbus_name = "sysbus-m48t08",
|
||||
.bus_name = "sysbus-m48t08",
|
||||
.model = 8,
|
||||
.size = 0x2000,
|
||||
},{
|
||||
.sysbus_name = "sysbus-m48t59",
|
||||
.model = 59,
|
||||
.size = 0x2000,
|
||||
},{
|
||||
.isa_name = "isa-m48t59",
|
||||
.bus_name = "sysbus-m48t59",
|
||||
.model = 59,
|
||||
.size = 0x2000,
|
||||
}
|
||||
|
@ -248,7 +182,7 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
|
|||
}
|
||||
|
||||
/* Direct access to NVRAM */
|
||||
static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
|
||||
void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
|
||||
{
|
||||
struct tm tm;
|
||||
int tmp;
|
||||
|
@ -413,7 +347,7 @@ static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
|
|||
}
|
||||
}
|
||||
|
||||
static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
|
||||
uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
|
||||
{
|
||||
struct tm tm;
|
||||
uint32_t retval = 0xFF;
|
||||
|
@ -517,11 +451,6 @@ static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
|
|||
return retval;
|
||||
}
|
||||
|
||||
static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
|
||||
{
|
||||
NVRAM->lock ^= 1 << lock;
|
||||
}
|
||||
|
||||
/* IO access to NVRAM */
|
||||
static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
|
||||
unsigned size)
|
||||
|
@ -639,7 +568,7 @@ static const VMStateDescription vmstate_m48t59 = {
|
|||
}
|
||||
};
|
||||
|
||||
static void m48t59_reset_common(M48t59State *NVRAM)
|
||||
void m48t59_reset_common(M48t59State *NVRAM)
|
||||
{
|
||||
NVRAM->addr = 0;
|
||||
NVRAM->lock = 0;
|
||||
|
@ -650,14 +579,6 @@ static void m48t59_reset_common(M48t59State *NVRAM)
|
|||
timer_del(NVRAM->wd_timer);
|
||||
}
|
||||
|
||||
static void m48t59_reset_isa(DeviceState *d)
|
||||
{
|
||||
M48txxISAState *isa = M48TXX_ISA(d);
|
||||
M48t59State *NVRAM = &isa->state;
|
||||
|
||||
m48t59_reset_common(NVRAM);
|
||||
}
|
||||
|
||||
static void m48t59_reset_sysbus(DeviceState *d)
|
||||
{
|
||||
M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
|
||||
|
@ -666,7 +587,7 @@ static void m48t59_reset_sysbus(DeviceState *d)
|
|||
m48t59_reset_common(NVRAM);
|
||||
}
|
||||
|
||||
static const MemoryRegionOps m48t59_io_ops = {
|
||||
const MemoryRegionOps m48t59_io_ops = {
|
||||
.read = NVRAM_readb,
|
||||
.write = NVRAM_writeb,
|
||||
.impl = {
|
||||
|
@ -685,14 +606,13 @@ Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
|||
SysBusDevice *s;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
if (!m48txx_info[i].sysbus_name ||
|
||||
m48txx_info[i].size != size ||
|
||||
m48txx_info[i].model != model) {
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
|
||||
if (m48txx_sysbus_info[i].size != size ||
|
||||
m48txx_sysbus_info[i].model != model) {
|
||||
continue;
|
||||
}
|
||||
|
||||
dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
|
||||
dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name);
|
||||
qdev_prop_set_int32(dev, "base-year", base_year);
|
||||
qdev_init_nofail(dev);
|
||||
s = SYS_BUS_DEVICE(dev);
|
||||
|
@ -712,31 +632,7 @@ Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
|||
return NULL;
|
||||
}
|
||||
|
||||
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int base_year, int model)
|
||||
{
|
||||
DeviceState *dev;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
if (!m48txx_info[i].isa_name ||
|
||||
m48txx_info[i].size != size ||
|
||||
m48txx_info[i].model != model) {
|
||||
continue;
|
||||
}
|
||||
|
||||
dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
|
||||
qdev_prop_set_uint32(dev, "iobase", io_base);
|
||||
qdev_prop_set_int32(dev, "base-year", base_year);
|
||||
qdev_init_nofail(dev);
|
||||
return NVRAM(dev);
|
||||
}
|
||||
|
||||
assert(false);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void m48t59_realize_common(M48t59State *s, Error **errp)
|
||||
void m48t59_realize_common(M48t59State *s, Error **errp)
|
||||
{
|
||||
s->buffer = g_malloc0(s->size);
|
||||
if (s->model == 59) {
|
||||
|
@ -748,23 +644,6 @@ static void m48t59_realize_common(M48t59State *s, Error **errp)
|
|||
vmstate_register(NULL, -1, &vmstate_m48t59, s);
|
||||
}
|
||||
|
||||
static void m48t59_isa_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
|
||||
ISADevice *isadev = ISA_DEVICE(dev);
|
||||
M48txxISAState *d = M48TXX_ISA(dev);
|
||||
M48t59State *s = &d->state;
|
||||
|
||||
s->model = u->info.model;
|
||||
s->size = u->info.size;
|
||||
isa_init_irq(isadev, &s->IRQ, 8);
|
||||
m48t59_realize_common(s, errp);
|
||||
memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
|
||||
if (d->io_base != 0) {
|
||||
isa_register_ioport(isadev, &d->io, d->io_base);
|
||||
}
|
||||
}
|
||||
|
||||
static int m48t59_init1(SysBusDevice *dev)
|
||||
{
|
||||
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
|
||||
|
@ -791,51 +670,6 @@ static int m48t59_init1(SysBusDevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
return m48t59_read(&d->state, addr);
|
||||
}
|
||||
|
||||
static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
m48t59_write(&d->state, addr, val);
|
||||
}
|
||||
|
||||
static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
|
||||
{
|
||||
M48txxISAState *d = M48TXX_ISA(obj);
|
||||
m48t59_toggle_lock(&d->state, lock);
|
||||
}
|
||||
|
||||
static Property m48t59_isa_properties[] = {
|
||||
DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
|
||||
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
static void m48txx_isa_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
NvramClass *nc = NVRAM_CLASS(klass);
|
||||
|
||||
dc->realize = m48t59_isa_realize;
|
||||
dc->reset = m48t59_reset_isa;
|
||||
dc->props = m48t59_isa_properties;
|
||||
nc->read = m48txx_isa_read;
|
||||
nc->write = m48txx_isa_write;
|
||||
nc->toggle_lock = m48txx_isa_toggle_lock;
|
||||
}
|
||||
|
||||
static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
|
||||
M48txxInfo *info = data;
|
||||
|
||||
u->info = *info;
|
||||
}
|
||||
|
||||
static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
|
||||
{
|
||||
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
|
||||
|
@ -899,18 +733,6 @@ static const TypeInfo m48txx_sysbus_type_info = {
|
|||
}
|
||||
};
|
||||
|
||||
static const TypeInfo m48txx_isa_type_info = {
|
||||
.name = TYPE_M48TXX_ISA,
|
||||
.parent = TYPE_ISA_DEVICE,
|
||||
.instance_size = sizeof(M48txxISAState),
|
||||
.abstract = true,
|
||||
.class_init = m48txx_isa_class_init,
|
||||
.interfaces = (InterfaceInfo[]) {
|
||||
{ TYPE_NVRAM },
|
||||
{ }
|
||||
}
|
||||
};
|
||||
|
||||
static void m48t59_register_types(void)
|
||||
{
|
||||
TypeInfo sysbus_type_info = {
|
||||
|
@ -918,29 +740,15 @@ static void m48t59_register_types(void)
|
|||
.class_size = sizeof(M48txxSysBusDeviceClass),
|
||||
.class_init = m48txx_sysbus_concrete_class_init,
|
||||
};
|
||||
TypeInfo isa_type_info = {
|
||||
.parent = TYPE_M48TXX_ISA,
|
||||
.class_size = sizeof(M48txxISADeviceClass),
|
||||
.class_init = m48txx_isa_concrete_class_init,
|
||||
};
|
||||
int i;
|
||||
|
||||
type_register_static(&nvram_info);
|
||||
type_register_static(&m48txx_sysbus_type_info);
|
||||
type_register_static(&m48txx_isa_type_info);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
if (m48txx_info[i].sysbus_name) {
|
||||
sysbus_type_info.name = m48txx_info[i].sysbus_name;
|
||||
sysbus_type_info.class_data = &m48txx_info[i];
|
||||
type_register(&sysbus_type_info);
|
||||
}
|
||||
|
||||
if (m48txx_info[i].isa_name) {
|
||||
isa_type_info.name = m48txx_info[i].isa_name;
|
||||
isa_type_info.class_data = &m48txx_info[i];
|
||||
type_register(&isa_type_info);
|
||||
}
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
|
||||
sysbus_type_info.name = m48txx_sysbus_info[i].bus_name;
|
||||
sysbus_type_info.class_data = &m48txx_sysbus_info[i];
|
||||
type_register(&sysbus_type_info);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue