target/i386: Leave TF in DisasContext.flags
It's just as easy to clear the flag with AND than assignment. In two cases the test for the bit can be folded together with the test for HF_INHIBIT_IRQ_MASK. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-26-richard.henderson@linaro.org>
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@ -101,7 +101,6 @@ typedef struct DisasContext {
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uint8_t vex_v; /* vex vvvv register, without 1's complement. */
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CCOp cc_op; /* current CC operation */
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bool cc_op_dirty;
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int tf; /* TF cpu flag */
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int jmp_opt; /* use direct block chaining for direct jumps */
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int repz_opt; /* optimize jumps within repz instructions */
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int mem_index; /* select memory access functions */
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@ -2656,7 +2655,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
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} else if (recheck_tf) {
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gen_helper_rechecking_single_step(cpu_env);
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tcg_gen_exit_tb(NULL, 0);
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} else if (s->tf) {
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} else if (s->flags & HF_TF_MASK) {
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gen_helper_single_step(cpu_env);
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} else if (jr) {
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tcg_gen_lookup_and_goto_ptr();
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@ -5540,7 +5539,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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if (s->base.is_jmp) {
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gen_jmp_im(s, s->pc - s->cs_base);
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if (reg == R_SS) {
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s->tf = 0;
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s->flags &= ~HF_TF_MASK;
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gen_eob_inhibit_irq(s, true);
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} else {
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gen_eob(s);
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@ -5606,7 +5605,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
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if (s->base.is_jmp) {
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gen_jmp_im(s, s->pc - s->cs_base);
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if (reg == R_SS) {
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s->tf = 0;
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s->flags &= ~HF_TF_MASK;
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gen_eob_inhibit_irq(s, true);
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} else {
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gen_eob(s);
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@ -8506,7 +8505,6 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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g_assert(LMA(dc) == ((flags & HF_LMA_MASK) != 0));
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g_assert(ADDSEG(dc) == ((flags & HF_ADDSEG_MASK) != 0));
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dc->tf = (flags >> TF_SHIFT) & 1;
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dc->cc_op = CC_OP_DYNAMIC;
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dc->cc_op_dirty = false;
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dc->popl_esp_hack = 0;
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@ -8521,8 +8519,8 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
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dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
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dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
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dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
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dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled ||
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(flags & HF_INHIBIT_IRQ_MASK));
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dc->jmp_opt = !(dc->base.singlestep_enabled ||
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(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
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/* Do not optimize repz jumps at all in icount mode, because
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rep movsS instructions are execured with different paths
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in !repz_opt and repz_opt modes. The first one was used
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@ -8597,7 +8595,7 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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pc_next = disas_insn(dc, cpu);
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if (dc->tf || (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {
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if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) {
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/* if single step mode, we generate only one instruction and
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generate an exception */
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/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
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