target-mips: Add delayed branch state to insn_start
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -130,6 +130,7 @@ struct CPUMIPSFPUContext {
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};
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};
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#define NB_MMU_MODES 3
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#define NB_MMU_MODES 3
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#define TARGET_INSN_START_EXTRA_WORDS 2
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
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struct CPUMIPSMVPContext {
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struct CPUMIPSMVPContext {
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@ -19562,6 +19562,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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ctx.CP0_Config1 = env->CP0_Config1;
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ctx.CP0_Config1 = env->CP0_Config1;
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ctx.tb = tb;
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ctx.tb = tb;
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ctx.bstate = BS_NONE;
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ctx.bstate = BS_NONE;
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ctx.btarget = 0;
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ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
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ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
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ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
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ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
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ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
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ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
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@ -19603,7 +19604,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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tcg_ctx.gen_opc_instr_start[lj] = 1;
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tcg_ctx.gen_opc_instr_start[lj] = 1;
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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tcg_ctx.gen_opc_icount[lj] = num_insns;
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}
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}
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tcg_gen_insn_start(ctx.pc);
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tcg_gen_insn_start(ctx.pc, ctx.hflags & MIPS_HFLAG_BMASK, ctx.btarget);
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num_insns++;
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num_insns++;
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if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
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if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
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