target-arm: Enable EL2 feature bit on A53 and A57
Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and Cortex-A57, since this is all now sufficiently implemented to work with the GICv3. We provide the usual CPU property to disable it for backwards compatibility with the older virt boards. In this commit, we disable the EL2 feature on the virt and ZynpMP boards, so there is no overall effect. Another commit will expose a board-level property to allow the user to enable EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-18-git-send-email-peter.maydell@linaro.org
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3f591a2022
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@ -1328,6 +1328,10 @@ static void machvirt_init(MachineState *machine)
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object_property_set_bool(cpuobj, false, "has_el3", NULL);
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object_property_set_bool(cpuobj, false, "has_el3", NULL);
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}
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}
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if (object_property_find(cpuobj, "has_el2", NULL)) {
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object_property_set_bool(cpuobj, false, "has_el2", NULL);
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}
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if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
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if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
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object_property_set_int(cpuobj, vms->psci_conduit,
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object_property_set_int(cpuobj, vms->psci_conduit,
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"psci-conduit", NULL);
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"psci-conduit", NULL);
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@ -258,6 +258,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
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object_property_set_bool(OBJECT(&s->apu_cpu[i]),
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object_property_set_bool(OBJECT(&s->apu_cpu[i]),
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s->secure, "has_el3", NULL);
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s->secure, "has_el3", NULL);
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object_property_set_bool(OBJECT(&s->apu_cpu[i]),
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false, "has_el2", NULL);
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object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
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object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR,
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"reset-cbar", &error_abort);
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"reset-cbar", &error_abort);
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object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
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object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized",
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@ -496,6 +496,9 @@ static Property arm_cpu_reset_hivecs_property =
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static Property arm_cpu_rvbar_property =
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static Property arm_cpu_rvbar_property =
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DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
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DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
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static Property arm_cpu_has_el2_property =
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DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
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static Property arm_cpu_has_el3_property =
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static Property arm_cpu_has_el3_property =
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DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
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DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
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@ -546,6 +549,11 @@ static void arm_cpu_post_init(Object *obj)
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#endif
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#endif
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}
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
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&error_abort);
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}
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if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
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if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
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qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
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&error_abort);
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&error_abort);
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@ -694,6 +702,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu->id_aa64pfr0 &= ~0xf000;
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cpu->id_aa64pfr0 &= ~0xf000;
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}
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}
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if (!cpu->has_el2) {
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unset_feature(env, ARM_FEATURE_EL2);
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}
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if (!cpu->has_pmu || !kvm_enabled()) {
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if (!cpu->has_pmu || !kvm_enabled()) {
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cpu->has_pmu = false;
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cpu->has_pmu = false;
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unset_feature(env, ARM_FEATURE_PMU);
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unset_feature(env, ARM_FEATURE_PMU);
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@ -577,6 +577,8 @@ struct ARMCPU {
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bool start_powered_off;
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bool start_powered_off;
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/* CPU currently in PSCI powered-off state */
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/* CPU currently in PSCI powered-off state */
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bool powered_off;
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bool powered_off;
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/* CPU has virtualization extension */
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bool has_el2;
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/* CPU has security extension */
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/* CPU has security extension */
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bool has_el3;
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bool has_el3;
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/* CPU has PMU (Performance Monitor Unit) */
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/* CPU has PMU (Performance Monitor Unit) */
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@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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@ -169,6 +170,7 @@ static void aarch64_a53_initfn(Object *obj)
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
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