x86_64 support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1371 c046a42c-6fe2-441c-8c8c-71466251a162
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07f4ddbf7e
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76
kqemu.c
76
kqemu.c
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@ -45,6 +45,11 @@
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#include <fcntl.h>
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#include "kqemu/kqemu.h"
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/* compatibility stuff */
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#ifndef KQEMU_RET_SYSCALL
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#define KQEMU_RET_SYSCALL 0x0300 /* syscall insn */
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#endif
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#ifdef _WIN32
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#define KQEMU_DEVICE "\\\\.\\kqemu"
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#else
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@ -71,6 +76,12 @@ extern uint32_t **l1_phys_map;
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
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: "0" (index))
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#ifdef __x86_64__
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static int is_cpuid_supported(void)
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{
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return 1;
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}
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#else
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static int is_cpuid_supported(void)
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{
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int v0, v1;
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@ -87,6 +98,7 @@ static int is_cpuid_supported(void)
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: "cc");
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return (v0 != v1);
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}
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#endif
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static void kqemu_update_cpuid(CPUState *env)
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{
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@ -231,8 +243,8 @@ struct fpxstate {
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uint32_t mxcsr;
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uint32_t mxcsr_mask;
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uint8_t fpregs1[8 * 16];
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uint8_t xmm_regs[8 * 16];
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uint8_t dummy2[224];
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uint8_t xmm_regs[16 * 16];
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uint8_t dummy2[96];
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};
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static struct fpxstate fpx1 __attribute__((aligned(16)));
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@ -308,7 +320,7 @@ static void restore_native_fp_fxrstor(CPUState *env)
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fp->mxcsr = env->mxcsr;
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/* XXX: check if DAZ is not available */
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fp->mxcsr_mask = 0xffff;
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memcpy(fp->xmm_regs, env->xmm_regs, 8 * 16);
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memcpy(fp->xmm_regs, env->xmm_regs, CPU_NB_REGS * 16);
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}
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asm volatile ("fxrstor %0" : "=m" (*fp));
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}
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@ -334,7 +346,7 @@ static void save_native_fp_fxsave(CPUState *env)
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}
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if (env->cpuid_features & CPUID_SSE) {
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env->mxcsr = fp->mxcsr;
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memcpy(env->xmm_regs, fp->xmm_regs, 8 * 16);
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memcpy(env->xmm_regs, fp->xmm_regs, CPU_NB_REGS * 16);
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}
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/* we must restore the default rounding state */
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@ -343,6 +355,55 @@ static void save_native_fp_fxsave(CPUState *env)
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asm volatile("fldcw %0" : : "m" (fpuc));
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}
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static int do_syscall(CPUState *env,
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struct kqemu_cpu_state *kenv)
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{
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int selector;
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selector = (env->star >> 32) & 0xffff;
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#ifdef __x86_64__
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if (env->hflags & HF_LMA_MASK) {
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env->regs[R_ECX] = kenv->next_eip;
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env->regs[11] = env->eflags;
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cpu_x86_set_cpl(env, 0);
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cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK);
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cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_W_MASK | DESC_A_MASK);
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env->eflags &= ~env->fmask;
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if (env->hflags & HF_CS64_MASK)
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env->eip = env->lstar;
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else
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env->eip = env->cstar;
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} else
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#endif
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{
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env->regs[R_ECX] = (uint32_t)kenv->next_eip;
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cpu_x86_set_cpl(env, 0);
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cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
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0, 0xffffffff,
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DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
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DESC_S_MASK |
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DESC_W_MASK | DESC_A_MASK);
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env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
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env->eip = (uint32_t)env->star;
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}
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return 2;
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}
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int kqemu_cpu_exec(CPUState *env)
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{
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struct kqemu_cpu_state kcpu_state, *kenv = &kcpu_state;
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@ -370,6 +431,9 @@ int kqemu_cpu_exec(CPUState *env)
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kenv->cr3 = env->cr[3];
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kenv->cr4 = env->cr[4];
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kenv->a20_mask = env->a20_mask;
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#ifdef __x86_64__
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kenv->efer = env->efer;
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#endif
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if (env->dr[7] & 0xff) {
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kenv->dr7 = env->dr[7];
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kenv->dr0 = env->dr[0];
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@ -435,6 +499,10 @@ int kqemu_cpu_exec(CPUState *env)
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fprintf(logfile, "kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
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}
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#endif
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if (ret == KQEMU_RET_SYSCALL) {
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/* syscall instruction */
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return do_syscall(env, kenv);
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} else
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if ((ret & 0xff00) == KQEMU_RET_INT) {
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env->exception_index = ret & 0xff;
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env->error_code = 0;
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