target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
Convert the VCVTA/VCVTN/VCVTP/VCVTM instructions to decodetree. trans_VCVT() is temporarily left in translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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@ -3340,12 +3340,31 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
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return true;
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}
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static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
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int rounding)
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static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
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{
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bool is_signed = extract32(insn, 7, 1);
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TCGv_ptr fpst = get_fpstatus_ptr(0);
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uint32_t rd, rm;
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bool dp = a->dp;
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TCGv_ptr fpst;
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TCGv_i32 tcg_rmode, tcg_shift;
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int rounding = fp_decode_rm[a->rm];
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bool is_signed = a->op;
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if (!dc_isar_feature(aa32_vcvt_dr, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
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return false;
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}
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rd = a->vd;
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rm = a->vm;
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if (!vfp_access_check(s)) {
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return true;
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}
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fpst = get_fpstatus_ptr(0);
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tcg_shift = tcg_const_i32(0);
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@ -3355,10 +3374,6 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
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if (dp) {
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TCGv_i64 tcg_double, tcg_res;
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TCGv_i32 tcg_tmp;
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/* Rd is encoded as a single precision register even when the source
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* is double precision.
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*/
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rd = ((rd << 1) & 0x1e) | ((rd >> 4) & 0x1);
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tcg_double = tcg_temp_new_i64();
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tcg_res = tcg_temp_new_i64();
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tcg_tmp = tcg_temp_new_i32();
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@ -3395,28 +3410,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
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tcg_temp_free_ptr(fpst);
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return 0;
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}
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static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
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{
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uint32_t rd, rm, dp = extract32(insn, 8, 1);
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if (dp) {
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VFP_DREG_D(rd, insn);
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VFP_DREG_M(rm, insn);
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} else {
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rd = VFP_SREG_D(insn);
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rm = VFP_SREG_M(insn);
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}
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if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&
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dc_isar_feature(aa32_vcvt_dr, s)) {
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/* VCVTA, VCVTN, VCVTP, VCVTM */
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int rounding = fp_decode_rm[extract32(insn, 16, 2)];
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return handle_vcvt(insn, rd, rm, dp, rounding);
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}
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return 1;
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return true;
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}
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/*
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@ -3452,6 +3446,15 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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}
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}
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if (extract32(insn, 28, 4) == 0xf) {
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/*
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* Encodings with T=1 (Thumb) or unconditional (ARM): these
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* were all handled by the decodetree decoder, so any insn
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* patterns which get here must be UNDEF.
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*/
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return 1;
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}
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/*
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* FIXME: this access check should not take precedence over UNDEF
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* for invalid encodings; we will generate incorrect syndrome information
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@ -3468,15 +3471,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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return 0;
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}
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if (extract32(insn, 28, 4) == 0xf) {
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/*
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* Encodings with T=1 (Thumb) or unconditional (ARM):
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* only used for the "miscellaneous VFP features" added in v8A
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* and v7M (and gated on the MVFR2.FPMisc field).
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*/
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return disas_vfp_misc_insn(s, insn);
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}
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dp = ((insn & 0xf00) == 0xb00);
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switch ((insn >> 24) & 0xf) {
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case 0xe:
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@ -55,3 +55,9 @@ VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
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vm=%vm_sp vd=%vd_sp dp=0
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VRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \
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vm=%vm_dp vd=%vd_dp dp=1
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# VCVT float to int with specified rounding mode; Vd is always single-precision
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VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
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vm=%vm_sp vd=%vd_sp dp=0
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VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
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vm=%vm_dp vd=%vd_sp dp=1
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