openpic: don't crash on a register access without a CPU context
If we access a register via the QEMU memory inspection commands (e.g. "xp") rather than from guest code, we won't have a CPU context. Gracefully fail to access the register in that case, rather than crashing. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
parent
a26a7b3833
commit
c3203fa5b2
16
hw/openpic.c
16
hw/openpic.c
|
@ -161,7 +161,11 @@ static inline int test_bit(uint32_t *field, int bit)
|
||||||
|
|
||||||
static int get_current_cpu(void)
|
static int get_current_cpu(void)
|
||||||
{
|
{
|
||||||
return cpu_single_env->cpu_index;
|
if (!cpu_single_env) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cpu_single_env->cpu_index;
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
|
static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
|
||||||
|
@ -810,6 +814,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
|
||||||
|
|
||||||
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
|
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
|
||||||
addr, val);
|
addr, val);
|
||||||
|
|
||||||
|
if (idx < 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
if (addr & 0xF)
|
if (addr & 0xF)
|
||||||
return;
|
return;
|
||||||
dst = &opp->dst[idx];
|
dst = &opp->dst[idx];
|
||||||
|
@ -875,6 +884,11 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
|
||||||
|
|
||||||
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
|
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
|
||||||
retval = 0xFFFFFFFF;
|
retval = 0xFFFFFFFF;
|
||||||
|
|
||||||
|
if (idx < 0) {
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
if (addr & 0xF)
|
if (addr & 0xF)
|
||||||
return retval;
|
return retval;
|
||||||
dst = &opp->dst[idx];
|
dst = &opp->dst[idx];
|
||||||
|
|
Loading…
Reference in a new issue