From c36c65ea3c35b309d524c05a1c05fdeabf83ddd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= Date: Fri, 8 Jan 2021 11:08:16 +0200 Subject: [PATCH] target/arm: ARMv8.4-TTST extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds for the Small Translation tables extension in AArch64 state. Signed-off-by: Rémi Denis-Courmont Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 15 +++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7e6c881a7e..ad37ff61c6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3936,6 +3936,11 @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; } +static inline bool isar_feature_aa64_st(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index d077dd9ef5..5ab3f5ace3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10842,7 +10842,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; bool epd, hpd, using16k, using64k; - int select, tsz, tbi; + int select, tsz, tbi, max_tsz; if (!regime_has_2_ranges(mmu_idx)) { select = 0; @@ -10877,7 +10877,14 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, hpd = extract64(tcr, 42, 1); } } - tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ + + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + max_tsz = 48 - using64k; + } else { + max_tsz = 39; + } + + tsz = MIN(tsz, max_tsz); tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ /* Present TBI as a composite with TBID. */ @@ -11096,6 +11103,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, if (!aarch64 || stride == 9) { /* AArch32 or 4KB pages */ startlevel = 2 - sl0; + + if (cpu_isar_feature(aa64_st, cpu)) { + startlevel &= 3; + } } else { /* 16KB or 64KB pages */ startlevel = 3 - sl0;