target/mips: Avoid case statements formulated by ranges - part 2
Remove "range style" case statements to make code analysis easier. This patch handles cases when the values in the range in question were not properly defined. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <amarkovic@wavecomp.com>
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@ -902,8 +902,21 @@ enum {
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OPC_MTTR = (0x0C << 21) | OPC_CP0,
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OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
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OPC_C0 = (0x10 << 21) | OPC_CP0,
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OPC_C0_FIRST = (0x10 << 21) | OPC_CP0,
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OPC_C0_LAST = (0x1F << 21) | OPC_CP0,
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OPC_C0_1 = (0x11 << 21) | OPC_CP0,
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OPC_C0_2 = (0x12 << 21) | OPC_CP0,
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OPC_C0_3 = (0x13 << 21) | OPC_CP0,
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OPC_C0_4 = (0x14 << 21) | OPC_CP0,
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OPC_C0_5 = (0x15 << 21) | OPC_CP0,
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OPC_C0_6 = (0x16 << 21) | OPC_CP0,
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OPC_C0_7 = (0x17 << 21) | OPC_CP0,
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OPC_C0_8 = (0x18 << 21) | OPC_CP0,
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OPC_C0_9 = (0x19 << 21) | OPC_CP0,
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OPC_C0_A = (0x1A << 21) | OPC_CP0,
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OPC_C0_B = (0x1B << 21) | OPC_CP0,
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OPC_C0_C = (0x1C << 21) | OPC_CP0,
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OPC_C0_D = (0x1D << 21) | OPC_CP0,
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OPC_C0_E = (0x1E << 21) | OPC_CP0,
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OPC_C0_F = (0x1F << 21) | OPC_CP0,
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};
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/* MFMC0 opcodes */
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@ -12490,10 +12503,22 @@ enum {
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/* PCREL Instructions perform PC-Relative address calculation. bits 20..16 */
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enum {
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ADDIUPC_00 = 0x00,
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ADDIUPC_01 = 0x01,
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ADDIUPC_02 = 0x02,
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ADDIUPC_03 = 0x03,
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ADDIUPC_04 = 0x04,
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ADDIUPC_05 = 0x05,
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ADDIUPC_06 = 0x06,
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ADDIUPC_07 = 0x07,
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AUIPC = 0x1e,
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ALUIPC = 0x1f,
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LWPC_08 = 0x08,
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LWPC_09 = 0x09,
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LWPC_0A = 0x0A,
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LWPC_0B = 0x0B,
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LWPC_0C = 0x0C,
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LWPC_0D = 0x0D,
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LWPC_0E = 0x0E,
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LWPC_0F = 0x0F,
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};
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@ -12928,12 +12953,16 @@ enum {
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R6_LWM16 = 0x02,
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R6_JRC16 = 0x03,
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MOVEP = 0x04,
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MOVEP_05 = 0x05,
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MOVEP_06 = 0x06,
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MOVEP_07 = 0x07,
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R6_XOR16 = 0x08,
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R6_OR16 = 0x09,
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R6_SWM16 = 0x0a,
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JALRC16 = 0x0b,
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MOVEP_0C = 0x0c,
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MOVEP_0D = 0x0d,
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MOVEP_0E = 0x0e,
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MOVEP_0F = 0x0f,
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JRCADDIUSP = 0x13,
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R6_BREAK16 = 0x1b,
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@ -13251,8 +13280,14 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
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gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
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}
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break;
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case MOVEP ... MOVEP_07:
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case MOVEP_0C ... MOVEP_0F:
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case MOVEP:
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case MOVEP_05:
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case MOVEP_06:
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case MOVEP_07:
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case MOVEP_0C:
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case MOVEP_0D:
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case MOVEP_0E:
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case MOVEP_0F:
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{
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int enc_dest = uMIPS_RD(ctx->opcode);
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int enc_rt = uMIPS_RS2(ctx->opcode);
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@ -15230,7 +15265,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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if (ctx->insn_flags & ISA_MIPS32R6) {
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/* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
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switch ((ctx->opcode >> 16) & 0x1f) {
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case ADDIUPC_00 ... ADDIUPC_07:
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case ADDIUPC_00:
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case ADDIUPC_01:
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case ADDIUPC_02:
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case ADDIUPC_03:
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case ADDIUPC_04:
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case ADDIUPC_05:
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case ADDIUPC_06:
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case ADDIUPC_07:
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gen_pcrel(ctx, OPC_ADDIUPC, ctx->base.pc_next & ~0x3, rt);
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break;
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case AUIPC:
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@ -15239,7 +15281,14 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
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case ALUIPC:
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gen_pcrel(ctx, OPC_ALUIPC, ctx->base.pc_next, rt);
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break;
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case LWPC_08 ... LWPC_0F:
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case LWPC_08:
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case LWPC_09:
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case LWPC_0A:
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case LWPC_0B:
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case LWPC_0C:
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case LWPC_0D:
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case LWPC_0E:
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case LWPC_0F:
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gen_pcrel(ctx, R6_OPC_LWPC, ctx->base.pc_next & ~0x3, rt);
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break;
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default:
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@ -19790,7 +19839,22 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_cp0(env, ctx, op1, rt, rd);
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#endif /* !CONFIG_USER_ONLY */
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break;
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case OPC_C0_FIRST ... OPC_C0_LAST:
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case OPC_C0:
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case OPC_C0_1:
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case OPC_C0_2:
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case OPC_C0_3:
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case OPC_C0_4:
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case OPC_C0_5:
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case OPC_C0_6:
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case OPC_C0_7:
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case OPC_C0_8:
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case OPC_C0_9:
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case OPC_C0_A:
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case OPC_C0_B:
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case OPC_C0_C:
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case OPC_C0_D:
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case OPC_C0_E:
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case OPC_C0_F:
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#ifndef CONFIG_USER_ONLY
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gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
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#endif /* !CONFIG_USER_ONLY */
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