target/ppc: add ov32 flag in divide operations
Add helper_div_compute_ov() in the int_helper for updating the overflow flags. For Divide Word: SO, OV, and OV32 bits reflects overflow of the 32-bit result For Divide DoubleWord: SO, OV, and OV32 bits reflects overflow of the 64-bit result Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1021,6 +1021,9 @@ static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
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}
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if (compute_ov) {
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tcg_gen_extu_i32_tl(cpu_ov, t2);
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if (is_isa300(ctx)) {
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tcg_gen_extu_i32_tl(cpu_ov32, t2);
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}
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tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
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}
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tcg_temp_free_i32(t0);
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@ -1092,6 +1095,9 @@ static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
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}
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if (compute_ov) {
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tcg_gen_mov_tl(cpu_ov, t2);
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if (is_isa300(ctx)) {
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tcg_gen_mov_tl(cpu_ov32, t2);
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}
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tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
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}
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tcg_temp_free_i64(t0);
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@ -1110,10 +1116,10 @@ static void glue(gen_, name)(DisasContext *ctx)
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cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
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sign, compute_ov); \
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}
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/* divwu divwu. divwuo divwuo. */
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/* divdu divdu. divduo divduo. */
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GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
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GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
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/* divw divw. divwo divwo. */
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/* divd divd. divdo divdo. */
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GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
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GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
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