target-arm: Check undefined opcodes for SWP in A32 decoder
Make sure we are not treating architecturally Undefined instructions as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A specification. Bits [21:20] must be zero for this to be a SWP or SWPB. We also choose to UNDEF for the architecturally UNPREDICTABLE case of bits [11:8] not being zero. Signed-off-by: Onur Sahin <onursahin08@gmail.com> [PMM: tweaked commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -9237,11 +9237,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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}
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}
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tcg_temp_free_i32(addr);
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} else {
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} else if ((insn & 0x00300f00) == 0) {
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/* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
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* - SWP, SWPB
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*/
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TCGv taddr;
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TCGMemOp opc = s->be_data;
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/* SWP instruction */
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rm = (insn) & 0xf;
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if (insn & (1 << 22)) {
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@ -9259,6 +9262,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
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get_mem_index(s), opc);
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tcg_temp_free(taddr);
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store_reg(s, rd, tmp);
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} else {
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goto illegal_op;
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}
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}
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} else {
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