From 6797c3151095a50c959ad848c93850d907a71537 Mon Sep 17 00:00:00 2001 From: Nick Hudson Date: Tue, 23 Apr 2019 07:36:20 +0100 Subject: [PATCH 1/2] target/hppa: Implement Fast TLB Insert instructions These instructions are present on pcxl and pcxl2 machines, and are used by NetBSD and OpenBSD. See https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf page 13-9 (195/206) Signed-off-by: Nick Hudson Message-Id: <20190423063621.8203-2-nick.hudson@gmx.co.uk> [rth: Use extending loads, locally managed temporaries.] Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 3 +++ target/hppa/translate.c | 54 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 098370c2f0..f0dd71dd08 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -133,6 +133,9 @@ ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ sp=%assemble_sr3x data=0 +# pcxl and pcxl2 Fast TLB Insert instructions +ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 + pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ sp=%assemble_sr3x data=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7c03c62768..e1febdfea1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2518,6 +2518,60 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a) #endif } +/* + * Implement the pcxl and pcxl2 Fast TLB Insert instructions. + * See + * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf + * page 13-9 (195/206) + */ +static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) +{ + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + TCGv_tl addr, atl, stl; + TCGv_reg reg; + + nullify_over(ctx); + + /* + * FIXME: + * if (not (pcxl or pcxl2)) + * return gen_illegal(ctx); + * + * Note for future: these are 32-bit systems; no hppa64. + */ + + atl = tcg_temp_new_tl(); + stl = tcg_temp_new_tl(); + addr = tcg_temp_new_tl(); + + tcg_gen_ld32u_i64(stl, cpu_env, + a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) + : offsetof(CPUHPPAState, cr[CR_IIASQ])); + tcg_gen_ld32u_i64(atl, cpu_env, + a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) + : offsetof(CPUHPPAState, cr[CR_IIAOQ])); + tcg_gen_shli_i64(stl, stl, 32); + tcg_gen_or_tl(addr, atl, stl); + tcg_temp_free_tl(atl); + tcg_temp_free_tl(stl); + + reg = load_gpr(ctx, a->r); + if (a->addr) { + gen_helper_itlba(cpu_env, addr, reg); + } else { + gen_helper_itlbp(cpu_env, addr, reg); + } + tcg_temp_free_tl(addr); + + /* Exit TB for TLB change if mmu is enabled. */ + if (ctx->tb_flags & PSW_C) { + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + } + return nullify_end(ctx); +#endif +} + static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); From affdb7e6ba23f8160cb88e11f83db54a35f03d6b Mon Sep 17 00:00:00 2001 From: Nick Hudson Date: Tue, 23 Apr 2019 07:36:21 +0100 Subject: [PATCH 2/2] target/hppa: Always return EXCP_DMAR for protection id trap The EXCP_DMP trap is considered legacy. "In PA-RISC 1.1 (Second Edition) and later revisions, processors must use traps 26, 27,and 28 which provide equivalent functionality" Signed-off-by: Nick Hudson Message-Id: <20190423063621.8203-3-nick.hudson@gmx.co.uk> Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index c9b57d07c3..77fb544838 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -154,8 +154,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, if (unlikely(!(prot & type))) { /* The access isn't allowed -- Inst/Data Memory Protection Fault. */ - ret = (type & PAGE_EXEC ? EXCP_IMP : - prot & PAGE_READ ? EXCP_DMP : EXCP_DMAR); + ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; goto egress; }