target/arm: Convert T16 add/sub (3 low, 2 low and imm)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-52-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \
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STM 11000 ... ........ @ldstm
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LDM_t16 11001 ... ........ @ldstm
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# Add/subtract (three low registers)
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@addsub_3 ....... rm:3 rn:3 rd:3 \
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&s_rrr_shi %s shim=0 shty=0
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ADD_rrri 0001100 ... ... ... @addsub_3
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SUB_rrri 0001101 ... ... ... @addsub_3
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# Add/subtract (two low registers and immediate)
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@addsub_2i ....... imm:3 rn:3 rd:3 \
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&s_rri_rot %s rot=0
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ADD_rri 0001 110 ... ... ... @addsub_2i
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SUB_rri 0001 111 ... ... ... @addsub_2i
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@ -10691,31 +10691,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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* 0b0001_1xxx_xxxx_xxxx
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* - Add, subtract (three low registers)
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* - Add, subtract (two low registers and immediate)
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* In decodetree.
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*/
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rn = (insn >> 3) & 7;
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tmp = load_reg(s, rn);
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if (insn & (1 << 10)) {
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/* immediate */
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tmp2 = tcg_temp_new_i32();
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tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
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} else {
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/* reg */
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rm = (insn >> 6) & 7;
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tmp2 = load_reg(s, rm);
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}
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if (insn & (1 << 9)) {
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if (s->condexec_mask)
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tcg_gen_sub_i32(tmp, tmp, tmp2);
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else
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gen_sub_CC(tmp, tmp, tmp2);
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} else {
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if (s->condexec_mask)
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tcg_gen_add_i32(tmp, tmp, tmp2);
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else
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gen_add_CC(tmp, tmp, tmp2);
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}
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tcg_temp_free_i32(tmp2);
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store_reg(s, rd, tmp);
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goto illegal_op;
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} else {
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/* shift immediate */
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rm = (insn >> 3) & 7;
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