target/riscv: Introduce temporary in gen_add_uw()
Following the recent changes in translate.c, gen_add_uw() causes
failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these
regressions by introducing a temporary.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210911140016.834071-2-philipp.tomsich@vrull.eu
Fixes: 191d1dafae
("target/riscv: Add DisasExtend to gen_arith*")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3)
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static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_ext32u_tl(arg1, arg1);
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tcg_gen_add_tl(ret, arg1, arg2);
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TCGv t = tcg_temp_new();
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tcg_gen_ext32u_tl(t, arg1);
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tcg_gen_add_tl(ret, t, arg2);
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tcg_temp_free(t);
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}
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static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
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