ppc/xive: Improve 'info pic' support
Provide a better output of the XIVE END structures including the escalation information and extend the PowerNV machine 'info pic' command with a dump of the END EAS table used for escalations. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190718115420.19919-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1595,6 +1595,15 @@ void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon)
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}
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xive_end_pic_print_info(&end, i, mon);
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}
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monitor_printf(mon, "XIVE[%x] END Escalation %08x .. %08x\n", blk, 0,
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nr_ends - 1);
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for (i = 0; i < nr_ends; i++) {
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if (xive_router_get_end(xrtr, blk, i, &end)) {
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break;
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}
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xive_end_eas_pic_print_info(&end, i, mon);
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}
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}
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static void pnv_xive_reset(void *dev)
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@ -146,7 +146,6 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end,
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priority, qindex, qentries, qaddr_base, qgen);
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xive_end_queue_pic_print_info(end, 6, mon);
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monitor_printf(mon, "]");
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}
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void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon)
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@ -1158,6 +1158,7 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon)
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be32_to_cpu(qdata));
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qindex = (qindex + 1) & (qentries - 1);
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}
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monitor_printf(mon, "]");
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}
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void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon)
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@ -1168,24 +1169,36 @@ void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon)
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uint32_t qsize = xive_get_field32(END_W0_QSIZE, end->w0);
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uint32_t qentries = 1 << (qsize + 10);
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uint32_t nvt = xive_get_field32(END_W6_NVT_INDEX, end->w6);
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uint32_t nvt_blk = xive_get_field32(END_W6_NVT_BLOCK, end->w6);
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uint32_t nvt_idx = xive_get_field32(END_W6_NVT_INDEX, end->w6);
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uint8_t priority = xive_get_field32(END_W7_F0_PRIORITY, end->w7);
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uint8_t pq;
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if (!xive_end_is_valid(end)) {
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return;
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}
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monitor_printf(mon, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64
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"% 6d/%5d ^%d", end_idx,
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pq = xive_get_field32(END_W1_ESn, end->w1);
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monitor_printf(mon, " %08x %c%c %c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
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end_idx,
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pq & XIVE_ESB_VAL_P ? 'P' : '-',
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pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
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xive_end_is_valid(end) ? 'v' : '-',
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xive_end_is_enqueue(end) ? 'q' : '-',
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xive_end_is_notify(end) ? 'n' : '-',
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xive_end_is_backlog(end) ? 'b' : '-',
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xive_end_is_escalate(end) ? 'e' : '-',
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priority, nvt, qaddr_base, qindex, qentries, qgen);
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xive_end_is_uncond_escalation(end) ? 'u' : '-',
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xive_end_is_silent_escalation(end) ? 's' : '-',
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priority, nvt_blk, nvt_idx);
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xive_end_queue_pic_print_info(end, 6, mon);
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monitor_printf(mon, "]\n");
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if (qaddr_base) {
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monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d",
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qaddr_base, qindex, qentries, qgen);
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xive_end_queue_pic_print_info(end, 6, mon);
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}
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monitor_printf(mon, "\n");
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}
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static void xive_end_enqueue(XiveEND *end, uint32_t data)
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@ -1213,6 +1226,29 @@ static void xive_end_enqueue(XiveEND *end, uint32_t data)
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end->w1 = xive_set_field32(END_W1_PAGE_OFF, end->w1, qindex);
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}
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void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx,
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Monitor *mon)
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{
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XiveEAS *eas = (XiveEAS *) &end->w4;
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uint8_t pq;
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if (!xive_end_is_escalate(end)) {
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return;
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}
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pq = xive_get_field32(END_W1_ESe, end->w1);
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monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
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end_idx,
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pq & XIVE_ESB_VAL_P ? 'P' : '-',
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pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
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xive_eas_is_valid(eas) ? 'V' : ' ',
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xive_eas_is_masked(eas) ? 'M' : ' ',
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(uint8_t) xive_get_field64(EAS_END_BLOCK, eas->w),
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(uint32_t) xive_get_field64(EAS_END_INDEX, eas->w),
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(uint32_t) xive_get_field64(EAS_END_DATA, eas->w));
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}
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/*
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* XIVE Router (aka. Virtualization Controller or IVRE)
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*/
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@ -354,8 +354,6 @@ typedef struct XiveRouterClass {
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XiveTCTX *(*get_tctx)(XiveRouter *xrtr, CPUState *cs);
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} XiveRouterClass;
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void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
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int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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XiveEAS *eas);
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int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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@ -397,9 +395,6 @@ typedef struct XiveENDSource {
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*/
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#define XIVE_PRIORITY_MAX 7
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void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
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void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
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/*
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* XIVE Thread Interrupt Management Aera (TIMA)
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*
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@ -131,6 +131,8 @@ typedef struct XiveEAS {
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#define xive_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS_VALID)
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#define xive_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS_MASKED)
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void xive_eas_pic_print_info(XiveEAS *eas, uint32_t lisn, Monitor *mon);
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static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
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{
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return (be64_to_cpu(word) & mask) >> ctz64(mask);
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@ -221,6 +223,10 @@ static inline uint64_t xive_end_qaddr(XiveEND *end)
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be32_to_cpu(end->w3);
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}
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void xive_end_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
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void xive_end_queue_pic_print_info(XiveEND *end, uint32_t width, Monitor *mon);
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void xive_end_eas_pic_print_info(XiveEND *end, uint32_t end_idx, Monitor *mon);
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/* Notification Virtual Target (NVT) */
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typedef struct XiveNVT {
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uint32_t w0;
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