hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
Implement the function which signals virtual interrupts to the CPU as appropriate following CPU interface state changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-13-git-send-email-peter.maydell@linaro.org
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@ -352,6 +352,53 @@ static uint32_t maintenance_interrupt_state(GICv3CPUState *cs)
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static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
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{
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/* Tell the CPU about any pending virtual interrupts or
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* maintenance interrupts, following a change to the state
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* of the CPU interface relevant to virtual interrupts.
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*
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* CAUTION: this function will call qemu_set_irq() on the
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* CPU maintenance IRQ line, which is typically wired up
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* to the GIC as a per-CPU interrupt. This means that it
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* will recursively call back into the GIC code via
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* gicv3_redist_set_irq() and thus into the CPU interface code's
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* gicv3_cpuif_update(). It is therefore important that this
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* function is only called as the final action of a CPU interface
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* register write implementation, after all the GIC state
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* fields have been updated. gicv3_cpuif_update() also must
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* not cause this function to be called, but that happens
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* naturally as a result of there being no architectural
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* linkage between the physical and virtual GIC logic.
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*/
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int idx;
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int irqlevel = 0;
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int fiqlevel = 0;
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int maintlevel = 0;
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idx = hppvi_index(cs);
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trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
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if (idx >= 0) {
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uint64_t lr = cs->ich_lr_el2[idx];
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if (icv_hppi_can_preempt(cs, lr)) {
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/* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
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if (lr & ICH_LR_EL2_GROUP) {
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irqlevel = 1;
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} else {
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fiqlevel = 1;
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}
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}
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}
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if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) {
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maintlevel = maintenance_interrupt_state(cs);
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}
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trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,
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irqlevel, maintlevel);
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qemu_set_irq(cs->parent_vfiq, fiqlevel);
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qemu_set_irq(cs->parent_virq, irqlevel);
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qemu_set_irq(cs->maintenance_irq, maintlevel);
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}
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static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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@ -2480,6 +2527,8 @@ void gicv3_init_cpuif(GICv3State *s)
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&& cpu->gic_num_lrs) {
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int j;
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cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
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cs->num_list_regs = cpu->gic_num_lrs;
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cs->vpribits = cpu->gic_vpribits;
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cs->vprebits = cpu->gic_vprebits;
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@ -138,6 +138,8 @@ gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d rea
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gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu %x value 0x%" PRIx64
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gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu %x value 0x%" PRIx64
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gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu %x value 0x%" PRIx64
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gicv3_cpuif_virt_update(uint32_t cpuid, int idx) "GICv3 CPU i/f %x virt HPPI update LR index %d"
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gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel, int maintlevel) "GICv3 CPU i/f %x virt HPPI update: setting FIQ %d IRQ %d maintenance-irq %d"
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# hw/intc/arm_gicv3_dist.c
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gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
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@ -150,6 +150,7 @@ struct GICv3CPUState {
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qemu_irq parent_fiq;
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qemu_irq parent_virq;
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qemu_irq parent_vfiq;
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qemu_irq maintenance_irq;
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/* Redistributor */
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uint32_t level; /* Current IRQ level */
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