pseries: Minor cleanups to HPT management hypercalls
* Standardize on 'ptex' instead of 'pte_index' for HPTE index variables for consistency and brevity * Avoid variables named 'index'; shadowing index(3) from libc can lead to surprising bugs if the variable is removed, because compiler errors might not appear for remaining references * Clarify index calculations in h_enter() - we have two cases, H_EXACT where the exact HPTE slot is given, and !H_EXACT where we search for an empty slot within the hash bucket. Make the calculation more consistent between the cases. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
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@ -47,12 +47,12 @@ static bool has_spr(PowerPCCPU *cpu, int spr)
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return cpu->env.spr_cb[spr].name != NULL;
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}
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static inline bool valid_pte_index(CPUPPCState *env, target_ulong pte_index)
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static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
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{
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/*
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* hash value/pteg group index is normalized by htab_mask
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*/
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if (((pte_index & ~7ULL) / HPTES_PER_GROUP) & ~env->htab_mask) {
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if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~cpu->env.htab_mask) {
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return false;
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}
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return true;
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@ -77,14 +77,13 @@ static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr)
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static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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target_ulong opcode, target_ulong *args)
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong ptex = args[1];
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target_ulong pteh = args[2];
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target_ulong ptel = args[3];
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unsigned apshift;
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target_ulong raddr;
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target_ulong index;
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target_ulong slot;
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uint64_t token;
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apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
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@ -116,25 +115,26 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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pteh &= ~0x60ULL;
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if (!valid_pte_index(env, pte_index)) {
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if (!valid_ptex(cpu, ptex)) {
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return H_PARAMETER;
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}
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index = 0;
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slot = ptex & 7ULL;
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ptex = ptex & ~7ULL;
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7ULL;
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token = ppc_hash64_start_access(cpu, pte_index);
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for (; index < 8; index++) {
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if (!(ppc_hash64_load_hpte0(cpu, token, index) & HPTE64_V_VALID)) {
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token = ppc_hash64_start_access(cpu, ptex);
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for (slot = 0; slot < 8; slot++) {
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if (!(ppc_hash64_load_hpte0(cpu, token, slot) & HPTE64_V_VALID)) {
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break;
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}
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}
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ppc_hash64_stop_access(cpu, token);
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if (index == 8) {
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if (slot == 8) {
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return H_PTEG_FULL;
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}
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} else {
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token = ppc_hash64_start_access(cpu, pte_index);
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token = ppc_hash64_start_access(cpu, ptex);
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if (ppc_hash64_load_hpte0(cpu, token, 0) & HPTE64_V_VALID) {
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ppc_hash64_stop_access(cpu, token);
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return H_PTEG_FULL;
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@ -142,10 +142,9 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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ppc_hash64_stop_access(cpu, token);
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}
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ppc_hash64_store_hpte(cpu, pte_index + index,
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pteh | HPTE64_V_HPTE_DIRTY, ptel);
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ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
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args[0] = pte_index + index;
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args[0] = ptex + slot;
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return H_SUCCESS;
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}
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@ -161,11 +160,10 @@ static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
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target_ulong flags,
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target_ulong *vp, target_ulong *rp)
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{
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CPUPPCState *env = &cpu->env;
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uint64_t token;
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target_ulong v, r;
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if (!valid_pte_index(env, ptex)) {
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if (!valid_ptex(cpu, ptex)) {
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return REMOVE_PARM;
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}
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@ -191,11 +189,11 @@ static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong ptex = args[1];
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target_ulong avpn = args[2];
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RemoveResult ret;
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ret = remove_hpte(cpu, pte_index, avpn, flags,
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ret = remove_hpte(cpu, ptex, avpn, flags,
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&args[0], &args[1]);
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switch (ret) {
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@ -291,16 +289,16 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong ptex = args[1];
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target_ulong avpn = args[2];
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uint64_t token;
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target_ulong v, r;
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if (!valid_pte_index(env, pte_index)) {
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if (!valid_ptex(cpu, ptex)) {
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return H_PARAMETER;
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}
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token = ppc_hash64_start_access(cpu, pte_index);
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token = ppc_hash64_start_access(cpu, ptex);
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v = ppc_hash64_load_hpte0(cpu, token, 0);
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r = ppc_hash64_load_hpte1(cpu, token, 0);
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ppc_hash64_stop_access(cpu, token);
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@ -315,13 +313,13 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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r |= (flags << 55) & HPTE64_R_PP0;
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r |= (flags << 48) & HPTE64_R_KEY_HI;
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r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
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ppc_hash64_store_hpte(cpu, pte_index,
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ppc_hash64_store_hpte(cpu, ptex,
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(v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
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ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r);
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ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
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/* Flush the tlb */
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check_tlb_flush(env, true);
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/* Don't need a memory barrier, due to qemu's global lock */
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ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
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ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
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return H_SUCCESS;
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}
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@ -330,21 +328,21 @@ static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr,
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{
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CPUPPCState *env = &cpu->env;
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target_ulong flags = args[0];
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target_ulong pte_index = args[1];
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target_ulong ptex = args[1];
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uint8_t *hpte;
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int i, ridx, n_entries = 1;
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if (!valid_pte_index(env, pte_index)) {
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if (!valid_ptex(cpu, ptex)) {
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return H_PARAMETER;
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}
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if (flags & H_READ_4) {
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/* Clear the two low order bits */
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pte_index &= ~(3ULL);
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ptex &= ~(3ULL);
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n_entries = 4;
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}
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64);
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hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64);
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for (i = 0, ridx = 0; i < n_entries; i++) {
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args[ridx++] = ldq_p(hpte);
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