target/arm: Update sve reduction vs simd_desc
With the reduction operations, we intentionally increase maxsz to
the next power of 2, so as to fill out the reduction tree correctly.
Since e2e7168a21
, oprsz must equal maxsz, with exceptions for small
vectors, so this triggers an assertion for vector sizes > 32 that are
not themselves a power of 2.
Pass the power-of-two value in the simd_data field instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2896,7 +2896,7 @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
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} \
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uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
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{ \
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uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_maxsz(desc); \
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uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
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TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
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for (i = 0; i < oprsz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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@ -3440,7 +3440,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
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{
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unsigned vsz = vec_full_reg_size(s);
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unsigned p2vsz = pow2ceil(vsz);
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TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, p2vsz, 0));
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TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
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TCGv_ptr t_zn, t_pg, status;
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TCGv_i64 temp;
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