target-arm: fix SRS/RFE instructions
The encoding of 'IA' and 'DB' conditions was swapped. SRS instruction must store banked SPSR instead of CPSR at the specific address. Missing 'return' statement at the end of RFE handling. Fixed write-back code to reference correct registers. From: Hyeonsung Jang <hsjang@ok-labs.com> Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
parent
217aff9c76
commit
c67b6b719b
|
@ -5749,7 +5749,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||||
}
|
}
|
||||||
} else if ((insn & 0x0e5fffe0) == 0x084d0500) {
|
} else if ((insn & 0x0e5fffe0) == 0x084d0500) {
|
||||||
/* srs */
|
/* srs */
|
||||||
uint32_t offset;
|
int32_t offset;
|
||||||
if (IS_USER(s))
|
if (IS_USER(s))
|
||||||
goto illegal_op;
|
goto illegal_op;
|
||||||
ARCH(6);
|
ARCH(6);
|
||||||
|
@ -5763,8 +5763,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||||
i = (insn >> 23) & 3;
|
i = (insn >> 23) & 3;
|
||||||
switch (i) {
|
switch (i) {
|
||||||
case 0: offset = -4; break; /* DA */
|
case 0: offset = -4; break; /* DA */
|
||||||
case 1: offset = -8; break; /* DB */
|
case 1: offset = 0; break; /* IA */
|
||||||
case 2: offset = 0; break; /* IA */
|
case 2: offset = -8; break; /* DB */
|
||||||
case 3: offset = 4; break; /* IB */
|
case 3: offset = 4; break; /* IB */
|
||||||
default: abort();
|
default: abort();
|
||||||
}
|
}
|
||||||
|
@ -5772,32 +5772,32 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||||
tcg_gen_addi_i32(addr, addr, offset);
|
tcg_gen_addi_i32(addr, addr, offset);
|
||||||
tmp = load_reg(s, 14);
|
tmp = load_reg(s, 14);
|
||||||
gen_st32(tmp, addr, 0);
|
gen_st32(tmp, addr, 0);
|
||||||
tmp = new_tmp();
|
tmp = load_cpu_field(spsr);
|
||||||
gen_helper_cpsr_read(tmp);
|
|
||||||
tcg_gen_addi_i32(addr, addr, 4);
|
tcg_gen_addi_i32(addr, addr, 4);
|
||||||
gen_st32(tmp, addr, 0);
|
gen_st32(tmp, addr, 0);
|
||||||
if (insn & (1 << 21)) {
|
if (insn & (1 << 21)) {
|
||||||
/* Base writeback. */
|
/* Base writeback. */
|
||||||
switch (i) {
|
switch (i) {
|
||||||
case 0: offset = -8; break;
|
case 0: offset = -8; break;
|
||||||
case 1: offset = -4; break;
|
case 1: offset = 4; break;
|
||||||
case 2: offset = 4; break;
|
case 2: offset = -4; break;
|
||||||
case 3: offset = 0; break;
|
case 3: offset = 0; break;
|
||||||
default: abort();
|
default: abort();
|
||||||
}
|
}
|
||||||
if (offset)
|
if (offset)
|
||||||
tcg_gen_addi_i32(addr, tmp, offset);
|
tcg_gen_addi_i32(addr, addr, offset);
|
||||||
if (op1 == (env->uncached_cpsr & CPSR_M)) {
|
if (op1 == (env->uncached_cpsr & CPSR_M)) {
|
||||||
gen_movl_reg_T1(s, 13);
|
store_reg(s, 13, addr);
|
||||||
} else {
|
} else {
|
||||||
gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), cpu_T[1]);
|
gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), addr);
|
||||||
|
dead_tmp(addr);
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
dead_tmp(addr);
|
dead_tmp(addr);
|
||||||
}
|
}
|
||||||
} else if ((insn & 0x0e5fffe0) == 0x081d0a00) {
|
} else if ((insn & 0x0e5fffe0) == 0x081d0a00) {
|
||||||
/* rfe */
|
/* rfe */
|
||||||
uint32_t offset;
|
int32_t offset;
|
||||||
if (IS_USER(s))
|
if (IS_USER(s))
|
||||||
goto illegal_op;
|
goto illegal_op;
|
||||||
ARCH(6);
|
ARCH(6);
|
||||||
|
@ -5806,8 +5806,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||||
i = (insn >> 23) & 3;
|
i = (insn >> 23) & 3;
|
||||||
switch (i) {
|
switch (i) {
|
||||||
case 0: offset = -4; break; /* DA */
|
case 0: offset = -4; break; /* DA */
|
||||||
case 1: offset = -8; break; /* DB */
|
case 1: offset = 0; break; /* IA */
|
||||||
case 2: offset = 0; break; /* IA */
|
case 2: offset = -8; break; /* DB */
|
||||||
case 3: offset = 4; break; /* IB */
|
case 3: offset = 4; break; /* IB */
|
||||||
default: abort();
|
default: abort();
|
||||||
}
|
}
|
||||||
|
@ -5821,8 +5821,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||||
/* Base writeback. */
|
/* Base writeback. */
|
||||||
switch (i) {
|
switch (i) {
|
||||||
case 0: offset = -8; break;
|
case 0: offset = -8; break;
|
||||||
case 1: offset = -4; break;
|
case 1: offset = 4; break;
|
||||||
case 2: offset = 4; break;
|
case 2: offset = -4; break;
|
||||||
case 3: offset = 0; break;
|
case 3: offset = 0; break;
|
||||||
default: abort();
|
default: abort();
|
||||||
}
|
}
|
||||||
|
@ -5833,6 +5833,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||||
dead_tmp(addr);
|
dead_tmp(addr);
|
||||||
}
|
}
|
||||||
gen_rfe(s, tmp, tmp2);
|
gen_rfe(s, tmp, tmp2);
|
||||||
|
return;
|
||||||
} else if ((insn & 0x0e000000) == 0x0a000000) {
|
} else if ((insn & 0x0e000000) == 0x0a000000) {
|
||||||
/* branch link and change to thumb (blx <offset>) */
|
/* branch link and change to thumb (blx <offset>) */
|
||||||
int32_t offset;
|
int32_t offset;
|
||||||
|
|
Loading…
Reference in a new issue