haraldwolff/qemu-patch-raspberry4
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pcie_host: convert to memory API

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Assuming that mmcfg size cannot change at runtime.

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-15 17:17:25 +03:00 committed by Anthony Liguori
parent 689a1921ae
commit c76f990e8d
2 changed files with 31 additions and 79 deletions
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98
hw/pcie_host.c
View file

@ -22,6 +22,7 @@
#include "hw.h"
#include "pci.h"
#include "pcie_host.h"
#include "exec-memory.h"
/*
* PCI express mmcfig address
@ -52,9 +53,11 @@ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
static void pcie_mmcfg_data_write(PCIBus *s,
uint32_t mmcfg_addr, uint32_t val, int len)
static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
uint64_t val, unsigned len)
{
PCIExpressHost *e = opaque;
PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@ -72,8 +75,12 @@ static void pcie_mmcfg_data_write(PCIBus *s,
pci_host_config_write_common(pci_dev, addr, limit, val, len);
}
static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
static uint64_t pcie_mmcfg_data_read(void *opaque,
target_phys_addr_t mmcfg_addr,
unsigned len)
{
PCIExpressHost *e = opaque;
PCIBus *s = e->pci.bus;
PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
uint32_t addr;
uint32_t limit;
@ -91,72 +98,23 @@ static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t mmcfg_addr, int len)
return pci_host_config_read_common(pci_dev, addr, limit, len);
}
static void pcie_mmcfg_data_writeb(void *opaque,
target_phys_addr_t addr, uint32_t value)
{
PCIExpressHost *e = opaque;
pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
}
static void pcie_mmcfg_data_writew(void *opaque,
target_phys_addr_t addr, uint32_t value)
{
PCIExpressHost *e = opaque;
pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
}
static void pcie_mmcfg_data_writel(void *opaque,
target_phys_addr_t addr, uint32_t value)
{
PCIExpressHost *e = opaque;
pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
}
static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
{
PCIExpressHost *e = opaque;
return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
}
static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
{
PCIExpressHost *e = opaque;
return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
}
static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
{
PCIExpressHost *e = opaque;
return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
}
static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
{
pcie_mmcfg_data_writeb,
pcie_mmcfg_data_writew,
pcie_mmcfg_data_writel,
};
static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
{
pcie_mmcfg_data_readb,
pcie_mmcfg_data_readw,
pcie_mmcfg_data_readl,
static const MemoryRegionOps pcie_mmcfg_ops = {
.read = pcie_mmcfg_data_read,
.write = pcie_mmcfg_data_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
int pcie_host_init(PCIExpressHost *e)
int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
assert(!(size & (size - 1))); /* power of 2 */
assert(size >= PCIE_MMCFG_SIZE_MIN);
assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
e->mmio_index =
cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
DEVICE_NATIVE_ENDIAN);
if (e->mmio_index < 0) {
return -1;
}
e->size = size;
memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
@ -164,29 +122,23 @@ int pcie_host_init(PCIExpressHost *e)
void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
memory_region_del_subregion(get_system_memory(), &e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
void pcie_host_mmcfg_map(PCIExpressHost *e,
target_phys_addr_t addr, uint32_t size)
void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
{
assert(!(size & (size - 1))); /* power of 2 */
assert(size >= PCIE_MMCFG_SIZE_MIN);
assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = addr;
e->size = size;
cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
target_phys_addr_t addr, uint32_t size)
target_phys_addr_t addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
pcie_host_mmcfg_map(e, addr, size);
pcie_host_mmcfg_map(e, addr);
}
}

12
hw/pcie_host.h
View file

@ -22,6 +22,7 @@
#define PCIE_HOST_H
#include "pci_host.h"
#include "memory.h"
struct PCIExpressHost {
PCIHostState pci;
@ -34,16 +35,15 @@ struct PCIExpressHost {
/* the size of MMCONFIG area. It's host bridge dependent */
target_phys_addr_t size;
/* result of cpu_register_io_memory() to map MMCONFIG area */
int mmio_index;
/* MMCONFIG mmio area */
MemoryRegion mmio;
};
int pcie_host_init(PCIExpressHost *e);
int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
void pcie_host_mmcfg_map(PCIExpressHost *e,
target_phys_addr_t addr, uint32_t size);
void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
target_phys_addr_t addr, uint32_t size);
target_phys_addr_t addr);
#endif /* PCIE_HOST_H */