target/mips: Introduce decode tree bindings for MSA ASE
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE. We start by decoding: - the branch instructions, - all instructions based on the MSA opcode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201215225757.764263-20-f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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@ -1,4 +1,9 @@
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gen = [
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decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
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]
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mips_ss = ss.source_set()
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mips_ss = ss.source_set()
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mips_ss.add(gen)
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mips_ss.add(files(
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mips_ss.add(files(
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'cpu.c',
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'cpu.c',
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'gdbstub.c',
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'gdbstub.c',
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24
target/mips/msa32.decode
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24
target/mips/msa32.decode
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# MIPS SIMD Architecture Module instruction set
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#
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# Copyright (C) 2020 Philippe Mathieu-Daudé
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#
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# SPDX-License-Identifier: LGPL-2.1-or-later
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#
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# Reference:
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# MIPS Architecture for Programmers Volume IV-j
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# The MIPS32 SIMD Architecture Module, Revision 1.12
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# (Document Number: MD00866-2B-MSA32-AFP-01.12)
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#
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&msa_bz df wt s16
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@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
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@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
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BZ_V 010001 01011 ..... ................ @bz
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BNZ_V 010001 01111 ..... ................ @bz
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BZ_x 010001 110 .. ..... ................ @bz_df
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BNZ_x 010001 111 .. ..... ................ @bz_df
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MSA 011110 --------------------------
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@ -6,6 +6,7 @@
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* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
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* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
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* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
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* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
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* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
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* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
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* Copyright (c) 2020 Philippe Mathieu-Daudé
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*
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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*/
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@ -16,6 +17,9 @@
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#include "fpu_helper.h"
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#include "fpu_helper.h"
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#include "internal.h"
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#include "internal.h"
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/* Include the auto-generated decoder. */
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#include "decode-msa32.c.inc"
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#define OPC_MSA (0x1E << 26)
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#define OPC_MSA (0x1E << 26)
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#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
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@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
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return true;
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return true;
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}
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}
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static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
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{
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return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
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}
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static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
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{
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return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
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}
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static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
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static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
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{
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{
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check_msa_access(ctx);
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check_msa_access(ctx);
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@ -388,6 +402,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
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return true;
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return true;
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}
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}
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static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
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{
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return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
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}
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static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
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{
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return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
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}
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void gen_msa_branch(DisasContext *ctx, uint32_t op1)
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void gen_msa_branch(DisasContext *ctx, uint32_t op1)
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{
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{
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uint8_t df = (ctx->opcode >> 21) & 0x3;
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uint8_t df = (ctx->opcode >> 21) & 0x3;
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@ -2261,3 +2285,15 @@ void gen_msa(DisasContext *ctx)
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break;
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break;
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}
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}
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}
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}
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static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
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{
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gen_msa(ctx);
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return true;
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}
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bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
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{
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return decode_msa32(ctx, insn);
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}
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@ -177,4 +177,7 @@ void msa_translate_init(void);
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void gen_msa(DisasContext *ctx);
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void gen_msa(DisasContext *ctx);
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void gen_msa_branch(DisasContext *ctx, uint32_t op1);
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void gen_msa_branch(DisasContext *ctx, uint32_t op1);
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/* decodetree generated */
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bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
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#endif
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#endif
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