tcg-ia64: Implement deposit
Note that in the general reg=reg,reg case we're restricted to 16-bit insertions. This makes it easy to allow "any" constant as input, as post-truncation it will fit into the constant load insn for which we have room in the bundle. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -231,6 +231,7 @@ enum {
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OPC_CMP4_LTU_A6 = 0x1a400000000ull,
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OPC_CMP4_EQ_A6 = 0x1c400000000ull,
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OPC_DEP_I14 = 0x0ae00000000ull,
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OPC_DEP_I15 = 0x08000000000ull,
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OPC_DEP_Z_I12 = 0x0a600000000ull,
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OPC_EXTR_I11 = 0x0a400002000ull,
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OPC_EXTR_U_I11 = 0x0a400000000ull,
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@ -514,6 +515,18 @@ static inline uint64_t tcg_opc_i14(int qp, uint64_t opc, int r1, uint64_t imm,
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| (qp & 0x3f);
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}
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static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1, int r2,
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int r3, uint64_t pos, uint64_t len)
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{
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return opc
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| ((pos & 0x3f) << 31)
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| ((len & 0x0f) << 27)
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| ((r3 & 0x7f) << 20)
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| ((r2 & 0x7f) << 13)
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| ((r1 & 0x7f) << 6)
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| (qp & 0x3f);
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}
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static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
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{
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return opc
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@ -1325,6 +1338,37 @@ static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
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tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
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}
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static inline void tcg_out_deposit(TCGContext *s, TCGArg ret, TCGArg a1,
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TCGArg a2, int const_a2, int pos, int len)
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{
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uint64_t i1 = 0, i2 = 0;
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int cpos = 63 - pos, lm1 = len - 1;
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if (const_a2) {
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/* Truncate the value of a constant a2 to the width of the field. */
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int mask = (1u << len) - 1;
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a2 &= mask;
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if (a2 == 0 || a2 == mask) {
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/* 1-bit signed constant inserted into register. */
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i2 = tcg_opc_i14(TCG_REG_P0, OPC_DEP_I14, ret, a2, a1, cpos, lm1);
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} else {
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/* Otherwise, load any constant into a temporary. Do this into
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the first I slot to help out with cross-unit delays. */
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i1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
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TCG_REG_R2, a2, TCG_REG_R0);
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a2 = TCG_REG_R2;
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}
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}
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if (i2 == 0) {
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i2 = tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, ret, a2, a1, cpos, lm1);
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}
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tcg_out_bundle(s, (i1 ? mII : miI),
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tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
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i1 ? i1 : tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
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i2);
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}
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static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
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TCGArg arg2, int cmp4)
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{
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@ -2130,6 +2174,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_bswap64(s, args[0], args[1]);
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break;
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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tcg_out_deposit(s, args[0], args[1], args[2], const_args[2],
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args[3], args[4]);
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break;
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case INDEX_op_brcond_i32:
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tcg_out_brcond(s, args[2], args[0], const_args[0],
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args[1], const_args[1], args[3], 1);
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@ -2294,6 +2344,9 @@ static const TCGTargetOpDef ia64_op_defs[] = {
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{ INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
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{ INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } },
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{ INDEX_op_deposit_i32, { "r", "rZ", "ri" } },
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{ INDEX_op_deposit_i64, { "r", "rZ", "ri" } },
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{ INDEX_op_qemu_ld8u, { "r", "r" } },
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{ INDEX_op_qemu_ld8s, { "r", "r" } },
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{ INDEX_op_qemu_ld16u, { "r", "r" } },
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@ -133,8 +133,11 @@ typedef enum {
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_deposit_i64 0
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
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#define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
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/* optional instructions automatically implemented */
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#define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */
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