hw/timer: RX62N compare match timer (CMT)
renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200224141923.82118-16-ysato@users.sourceforge.jp> [PMD: Split from TMR, filled VMStateField for migration] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>stable-6.0
Yoshinori Sato
Philippe Mathieu-Daudé
parent
7adca78eda
commit
c7f37bafde
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@ -1972,10 +1972,10 @@ M: Yoshinori Sato <ysato@users.sourceforge.jp>
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R: Magnus Damm <magnus.damm@gmail.com>
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S: Maintained
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F: hw/char/sh_serial.c
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F: hw/timer/renesas_tmr.c
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F: hw/timer/renesas_*.c
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F: hw/timer/sh_timer.c
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F: include/hw/sh4/sh.h
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F: include/hw/timer/renesas_tmr.h
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F: include/hw/timer/renesas_*.h
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Renesas RX peripherals
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M: Yoshinori Sato <ysato@users.sourceforge.jp>
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@ -38,3 +38,6 @@ config CMSDK_APB_DUALTIMER
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config RENESAS_TMR
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bool
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config RENESAS_CMT
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bool
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@ -24,6 +24,7 @@ common-obj-$(CONFIG_OMAP) += omap_synctimer.o
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common-obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o
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common-obj-$(CONFIG_SH4) += sh_timer.o
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common-obj-$(CONFIG_RENESAS_TMR) += renesas_tmr.o
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common-obj-$(CONFIG_RENESAS_CMT) += renesas_cmt.o
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common-obj-$(CONFIG_DIGIC) += digic-timer.o
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common-obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o
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@ -0,0 +1,283 @@
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/*
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* Renesas 16bit Compare-match timer
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*
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* Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
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* (Rev.1.40 R01UH0033EJ0140)
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "hw/timer/renesas_cmt.h"
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#include "migration/vmstate.h"
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/*
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* +0 CMSTR - common control
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* +2 CMCR - ch0
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* +4 CMCNT - ch0
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* +6 CMCOR - ch0
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* +8 CMCR - ch1
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* +10 CMCNT - ch1
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* +12 CMCOR - ch1
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* If we think that the address of CH 0 has an offset of +2,
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* we can treat it with the same address as CH 1, so define it like that.
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*/
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REG16(CMSTR, 0)
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FIELD(CMSTR, STR0, 0, 1)
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FIELD(CMSTR, STR1, 1, 1)
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FIELD(CMSTR, STR, 0, 2)
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/* This addeess is channel offset */
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REG16(CMCR, 0)
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FIELD(CMCR, CKS, 0, 2)
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FIELD(CMCR, CMIE, 6, 1)
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REG16(CMCNT, 2)
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REG16(CMCOR, 4)
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static void update_events(RCMTState *cmt, int ch)
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{
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int64_t next_time;
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if ((cmt->cmstr & (1 << ch)) == 0) {
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/* count disable, so not happened next event. */
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return ;
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}
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next_time = cmt->cmcor[ch] - cmt->cmcnt[ch];
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next_time *= NANOSECONDS_PER_SECOND;
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next_time /= cmt->input_freq;
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/*
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* CKS -> div rate
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* 0 -> 8 (1 << 3)
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* 1 -> 32 (1 << 5)
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* 2 -> 128 (1 << 7)
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* 3 -> 512 (1 << 9)
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*/
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next_time *= 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2);
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next_time += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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timer_mod(&cmt->timer[ch], next_time);
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}
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static int64_t read_cmcnt(RCMTState *cmt, int ch)
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{
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int64_t delta, now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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if (cmt->cmstr & (1 << ch)) {
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delta = (now - cmt->tick[ch]);
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delta /= NANOSECONDS_PER_SECOND;
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delta /= cmt->input_freq;
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delta /= 1 << (3 + FIELD_EX16(cmt->cmcr[ch], CMCR, CKS) * 2);
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cmt->tick[ch] = now;
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return cmt->cmcnt[ch] + delta;
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} else {
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return cmt->cmcnt[ch];
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}
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}
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static uint64_t cmt_read(void *opaque, hwaddr offset, unsigned size)
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{
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RCMTState *cmt = opaque;
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int ch = offset / 0x08;
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uint64_t ret;
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if (offset == A_CMSTR) {
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ret = 0;
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ret = FIELD_DP16(ret, CMSTR, STR,
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FIELD_EX16(cmt->cmstr, CMSTR, STR));
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return ret;
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} else {
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offset &= 0x07;
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if (ch == 0) {
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offset -= 0x02;
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}
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switch (offset) {
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case A_CMCR:
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ret = 0;
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ret = FIELD_DP16(ret, CMCR, CKS,
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FIELD_EX16(cmt->cmstr, CMCR, CKS));
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ret = FIELD_DP16(ret, CMCR, CMIE,
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FIELD_EX16(cmt->cmstr, CMCR, CMIE));
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return ret;
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case A_CMCNT:
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return read_cmcnt(cmt, ch);
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case A_CMCOR:
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return cmt->cmcor[ch];
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}
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}
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qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PRIX " "
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"not implemented\n",
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offset);
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return UINT64_MAX;
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}
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static void start_stop(RCMTState *cmt, int ch, int st)
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{
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if (st) {
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update_events(cmt, ch);
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} else {
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timer_del(&cmt->timer[ch]);
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}
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}
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static void cmt_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
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{
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RCMTState *cmt = opaque;
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int ch = offset / 0x08;
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if (offset == A_CMSTR) {
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cmt->cmstr = FIELD_EX16(val, CMSTR, STR);
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start_stop(cmt, 0, FIELD_EX16(cmt->cmstr, CMSTR, STR0));
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start_stop(cmt, 1, FIELD_EX16(cmt->cmstr, CMSTR, STR1));
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} else {
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offset &= 0x07;
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if (ch == 0) {
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offset -= 0x02;
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}
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switch (offset) {
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case A_CMCR:
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cmt->cmcr[ch] = FIELD_DP16(cmt->cmcr[ch], CMCR, CKS,
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FIELD_EX16(val, CMCR, CKS));
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cmt->cmcr[ch] = FIELD_DP16(cmt->cmcr[ch], CMCR, CMIE,
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FIELD_EX16(val, CMCR, CMIE));
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break;
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case 2:
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cmt->cmcnt[ch] = val;
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break;
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case 4:
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cmt->cmcor[ch] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "renesas_cmt: Register 0x%" HWADDR_PRIX " "
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"not implemented\n",
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offset);
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return;
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}
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if (FIELD_EX16(cmt->cmstr, CMSTR, STR) & (1 << ch)) {
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update_events(cmt, ch);
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}
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}
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}
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static const MemoryRegionOps cmt_ops = {
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.write = cmt_write,
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.read = cmt_read,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 2,
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.max_access_size = 2,
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},
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.valid = {
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.min_access_size = 2,
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.max_access_size = 2,
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},
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};
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static void timer_events(RCMTState *cmt, int ch)
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{
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cmt->cmcnt[ch] = 0;
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cmt->tick[ch] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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update_events(cmt, ch);
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if (FIELD_EX16(cmt->cmcr[ch], CMCR, CMIE)) {
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qemu_irq_pulse(cmt->cmi[ch]);
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}
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}
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static void timer_event0(void *opaque)
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{
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RCMTState *cmt = opaque;
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timer_events(cmt, 0);
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}
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static void timer_event1(void *opaque)
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{
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RCMTState *cmt = opaque;
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timer_events(cmt, 1);
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}
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static void rcmt_reset(DeviceState *dev)
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{
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RCMTState *cmt = RCMT(dev);
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cmt->cmstr = 0;
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cmt->cmcr[0] = cmt->cmcr[1] = 0;
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cmt->cmcnt[0] = cmt->cmcnt[1] = 0;
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cmt->cmcor[0] = cmt->cmcor[1] = 0xffff;
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}
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static void rcmt_init(Object *obj)
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{
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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RCMTState *cmt = RCMT(obj);
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int i;
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memory_region_init_io(&cmt->memory, OBJECT(cmt), &cmt_ops,
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cmt, "renesas-cmt", 0x10);
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sysbus_init_mmio(d, &cmt->memory);
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for (i = 0; i < ARRAY_SIZE(cmt->cmi); i++) {
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sysbus_init_irq(d, &cmt->cmi[i]);
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}
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timer_init_ns(&cmt->timer[0], QEMU_CLOCK_VIRTUAL, timer_event0, cmt);
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timer_init_ns(&cmt->timer[1], QEMU_CLOCK_VIRTUAL, timer_event1, cmt);
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}
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static const VMStateDescription vmstate_rcmt = {
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.name = "rx-cmt",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT16(cmstr, RCMTState),
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VMSTATE_UINT16_ARRAY(cmcr, RCMTState, CMT_CH),
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VMSTATE_UINT16_ARRAY(cmcnt, RCMTState, CMT_CH),
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VMSTATE_UINT16_ARRAY(cmcor, RCMTState, CMT_CH),
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VMSTATE_INT64_ARRAY(tick, RCMTState, CMT_CH),
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VMSTATE_TIMER_ARRAY(timer, RCMTState, CMT_CH),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property rcmt_properties[] = {
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DEFINE_PROP_UINT64("input-freq", RCMTState, input_freq, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void rcmt_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_rcmt;
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dc->reset = rcmt_reset;
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device_class_set_props(dc, rcmt_properties);
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}
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static const TypeInfo rcmt_info = {
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.name = TYPE_RENESAS_CMT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RCMTState),
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.instance_init = rcmt_init,
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.class_init = rcmt_class_init,
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};
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static void rcmt_register_types(void)
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{
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type_register_static(&rcmt_info);
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}
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type_init(rcmt_register_types)
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@ -0,0 +1,40 @@
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/*
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* Renesas Compare-match timer Object
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_TIMER_RENESAS_CMT_H
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#define HW_TIMER_RENESAS_CMT_H
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#include "qemu/timer.h"
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#include "hw/sysbus.h"
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#define TYPE_RENESAS_CMT "renesas-cmt"
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#define RCMT(obj) OBJECT_CHECK(RCMTState, (obj), TYPE_RENESAS_CMT)
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enum {
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CMT_CH = 2,
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CMT_NR_IRQ = 1 * CMT_CH
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};
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typedef struct RCMTState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint64_t input_freq;
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MemoryRegion memory;
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uint16_t cmstr;
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uint16_t cmcr[CMT_CH];
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uint16_t cmcnt[CMT_CH];
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uint16_t cmcor[CMT_CH];
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int64_t tick[CMT_CH];
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qemu_irq cmi[CMT_CH];
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QEMUTimer timer[CMT_CH];
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} RCMTState;
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#endif
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Reference in New Issue