target/ppc: introduce avr_full_offset() function
All TCG vector operations require pointers to the base address of the vector rather than separate access to the top and bottom 64-bits. Convert the VMX TCG instructions to use a new avr_full_offset() function instead of avr64_offset() which can then itself be written as a simple wrapper onto vsr_full_offset(). This same function can also reused in cpu_avr_ptr() to avoid having more than one copy of the offset calculation logic. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20190307180520.13868-5-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -2598,14 +2598,24 @@ static inline int vsrl_offset(int i)
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return offsetof(CPUPPCState, vsr[i].u64[1]);
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return offsetof(CPUPPCState, vsr[i].u64[1]);
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}
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}
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static inline int vsr_full_offset(int i)
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{
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return offsetof(CPUPPCState, vsr[i].u64[0]);
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}
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static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
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static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
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{
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{
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return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
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return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
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}
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}
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static inline int avr_full_offset(int i)
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{
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return vsr_full_offset(i + 32);
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}
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static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
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static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
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{
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{
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return &env->vsr[32 + i];
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return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
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}
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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@ -10,7 +10,7 @@
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static inline TCGv_ptr gen_avr_ptr(int reg)
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static inline TCGv_ptr gen_avr_ptr(int reg)
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{
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{
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TCGv_ptr r = tcg_temp_new_ptr();
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TCGv_ptr r = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0]));
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tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
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return r;
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return r;
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}
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}
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@ -205,7 +205,7 @@ static void gen_mtvscr(DisasContext *ctx)
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}
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}
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val = tcg_temp_new_i32();
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val = tcg_temp_new_i32();
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bofs = avr64_offset(rB(ctx->opcode), true);
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bofs = avr_full_offset(rB(ctx->opcode));
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#ifdef HOST_WORDS_BIGENDIAN
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#ifdef HOST_WORDS_BIGENDIAN
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bofs += 3 * 4;
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bofs += 3 * 4;
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#endif
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#endif
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@ -284,9 +284,9 @@ static void glue(gen_, name)(DisasContext *ctx) \
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} \
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} \
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\
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\
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tcg_op(vece, \
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tcg_op(vece, \
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avr64_offset(rD(ctx->opcode), true), \
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avr_full_offset(rD(ctx->opcode)), \
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avr64_offset(rA(ctx->opcode), true), \
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avr_full_offset(rA(ctx->opcode)), \
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avr64_offset(rB(ctx->opcode), true), \
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avr_full_offset(rB(ctx->opcode)), \
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16, 16); \
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16, 16); \
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}
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}
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@ -578,10 +578,10 @@ static void glue(gen_, NAME)(DisasContext *ctx) \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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gen_exception(ctx, POWERPC_EXCP_VPU); \
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return; \
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return; \
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} \
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} \
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tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \
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tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \
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offsetof(CPUPPCState, vscr_sat), \
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offsetof(CPUPPCState, vscr_sat), \
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avr64_offset(rA(ctx->opcode), true), \
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avr_full_offset(rA(ctx->opcode)), \
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avr64_offset(rB(ctx->opcode), true), \
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avr_full_offset(rB(ctx->opcode)), \
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16, 16, &g); \
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16, 16, &g); \
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}
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}
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@ -755,7 +755,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
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return; \
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return; \
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} \
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} \
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simm = SIMM5(ctx->opcode); \
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simm = SIMM5(ctx->opcode); \
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tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \
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tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \
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}
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}
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GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
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GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12);
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@ -850,8 +850,8 @@ static void gen_vsplt(DisasContext *ctx, int vece)
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}
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}
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uimm = UIMM5(ctx->opcode);
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uimm = UIMM5(ctx->opcode);
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bofs = avr64_offset(rB(ctx->opcode), true);
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bofs = avr_full_offset(rB(ctx->opcode));
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dofs = avr64_offset(rD(ctx->opcode), true);
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dofs = avr_full_offset(rD(ctx->opcode));
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/* Experimental testing shows that hardware masks the immediate. */
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/* Experimental testing shows that hardware masks the immediate. */
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bofs += (uimm << vece) & 15;
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bofs += (uimm << vece) & 15;
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@ -10,11 +10,6 @@ static inline void set_vsrl(int n, TCGv_i64 src)
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tcg_gen_st_i64(src, cpu_env, vsrl_offset(n));
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tcg_gen_st_i64(src, cpu_env, vsrl_offset(n));
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}
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}
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static inline int vsr_full_offset(int n)
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{
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return offsetof(CPUPPCState, vsr[n].u64[0]);
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}
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static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
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static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
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{
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{
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if (n < 32) {
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if (n < 32) {
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