target-arm: Use mul[us]2 and add2 in umlal et al
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -2893,11 +2893,6 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
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return (a & mask) | (b & ~mask);
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return (a & mask) | (b & ~mask);
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}
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}
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uint32_t HELPER(logicq_cc)(uint64_t val)
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{
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return (val >> 32) | (val != 0);
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}
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/* VFP support. We follow the convention used for VFP instructions:
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/* VFP support. We follow the convention used for VFP instructions:
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Single precision routines have a "s" suffix, double precision a
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Single precision routines have a "s" suffix, double precision a
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"d" suffix. */
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"d" suffix. */
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@ -46,8 +46,6 @@ DEF_HELPER_3(usat16, i32, env, i32, i32)
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DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_1(logicq_cc, i32, i64)
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DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
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DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
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i32, i32, i32, i32)
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i32, i32, i32, i32)
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DEF_HELPER_2(exception, void, env, i32)
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DEF_HELPER_2(exception, void, env, i32)
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@ -6433,13 +6433,11 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
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tcg_temp_free_i64(tmp);
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tcg_temp_free_i64(tmp);
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}
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}
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/* Set N and Z flags from a 64-bit value. */
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/* Set N and Z flags from hi|lo. */
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static void gen_logicq_cc(TCGv_i64 val)
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static void gen_logicq_cc(TCGv lo, TCGv hi)
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{
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{
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TCGv tmp = tcg_temp_new_i32();
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tcg_gen_mov_i32(cpu_NF, hi);
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gen_helper_logicq_cc(tmp, val);
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tcg_gen_or_i32(cpu_ZF, lo, hi);
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gen_logic_CC(tmp);
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tcg_temp_free_i32(tmp);
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}
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}
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/* Load/Store exclusive instructions are implemented by remembering
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/* Load/Store exclusive instructions are implemented by remembering
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@ -7219,18 +7217,22 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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tmp = load_reg(s, rs);
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tmp = load_reg(s, rs);
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tmp2 = load_reg(s, rm);
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tmp2 = load_reg(s, rm);
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if (insn & (1 << 22)) {
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if (insn & (1 << 22)) {
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tmp64 = gen_muls_i64_i32(tmp, tmp2);
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tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2);
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} else {
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} else {
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tmp64 = gen_mulu_i64_i32(tmp, tmp2);
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tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2);
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}
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}
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if (insn & (1 << 21)) { /* mult accumulate */
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if (insn & (1 << 21)) { /* mult accumulate */
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gen_addq(s, tmp64, rn, rd);
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TCGv al = load_reg(s, rn);
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TCGv ah = load_reg(s, rd);
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tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah);
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tcg_temp_free(al);
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tcg_temp_free(ah);
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}
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}
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if (insn & (1 << 20)) {
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if (insn & (1 << 20)) {
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gen_logicq_cc(tmp64);
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gen_logicq_cc(tmp, tmp2);
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}
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}
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gen_storeq_reg(s, rn, rd, tmp64);
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store_reg(s, rn, tmp);
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tcg_temp_free_i64(tmp64);
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store_reg(s, rd, tmp2);
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break;
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break;
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default:
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default:
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goto illegal_op;
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goto illegal_op;
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