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ppc: Speed up dcbz

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Use tlb_vaddr_to_host to do a fast path single translate for
the whole cache line. Also make the reservation check match
the entire range.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Benjamin Herrenschmidt 2016-07-27 16:56:43 +10:00 committed by David Gibson
parent 22b56ee568
commit c9f82d013b
2 changed files with 29 additions and 28 deletions
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46
target-ppc/mem_helper.c
View file

@ -141,35 +141,39 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
} }
} }
static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size, void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t opcode)
uintptr_t raddr)
{ {
int i; target_ulong mask, dcbz_size = env->dcache_line_size;
uint32_t i;
addr &= ~(dcache_line_size - 1); void *haddr;
for (i = 0; i < dcache_line_size; i += 4) {
cpu_stl_data_ra(env, addr + i, 0, raddr);
}
if (env->reserve_addr == addr) {
env->reserve_addr = (target_ulong)-1ULL;
}
}
void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
{
int dcbz_size = env->dcache_line_size;
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
if (!is_dcbzl && /* Check for dcbz vs dcbzl on 970 */
(env->excp_model == POWERPC_EXCP_970) && if (env->excp_model == POWERPC_EXCP_970 &&
((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { !(opcode & 0x00200000) && ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
dcbz_size = 32; dcbz_size = 32;
} }
#endif #endif
/* XXX add e500mc support */ /* Align address */
mask = ~(dcbz_size - 1);
addr &= mask;
do_dcbz(env, addr, dcbz_size, GETPC()); /* Check reservation */
if ((env->reserve_addr & mask) == (addr & mask)) {
env->reserve_addr = (target_ulong)-1ULL;
}
/* Try fast path translate */
haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, env->dmmu_idx);
if (haddr) {
memset(haddr, 0, dcbz_size);
} else {
/* Slow path */
for (i = 0; i < dcbz_size; i += 8) {
cpu_stq_data_ra(env, addr + i, 0, GETPC());
}
}
} }
void helper_icbi(CPUPPCState *env, target_ulong addr) void helper_icbi(CPUPPCState *env, target_ulong addr)

11
target-ppc/translate.c
View file

@ -4088,18 +4088,15 @@ static void gen_dcbtls(DisasContext *ctx)
static void gen_dcbz(DisasContext *ctx) static void gen_dcbz(DisasContext *ctx)
{ {
TCGv tcgv_addr; TCGv tcgv_addr;
TCGv_i32 tcgv_is_dcbzl; TCGv_i32 tcgv_op;
int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
gen_set_access_type(ctx, ACCESS_CACHE); gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new(); tcgv_addr = tcg_temp_new();
tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr); gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
tcg_temp_free(tcgv_addr); tcg_temp_free(tcgv_addr);
tcg_temp_free_i32(tcgv_is_dcbzl); tcg_temp_free_i32(tcgv_op);
} }
/* dst / dstt */ /* dst / dstt */