target/mips: Let raise_mmu_exception() take MMUAccessType argument
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass MMUAccessType to raise_mmu_exception(). Let the prototype use it as argument, as it is stricter than an integer. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20210128144125.3696119-11-f4bug@amsat.org>
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@ -405,12 +405,12 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
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#endif /* !CONFIG_USER_ONLY */
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static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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int rw, int tlb_error)
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MMUAccessType access_type, int tlb_error)
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{
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CPUState *cs = env_cpu(env);
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int exception = 0, error_code = 0;
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if (rw == MMU_INST_FETCH) {
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if (access_type == MMU_INST_FETCH) {
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error_code |= EXCP_INST_NOTAVAIL;
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}
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@ -419,7 +419,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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case TLBRET_BADADDR:
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/* Reference to kernel address from user mode or supervisor mode */
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/* Reference to supervisor address from user mode */
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if (rw == MMU_DATA_STORE) {
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if (access_type == MMU_DATA_STORE) {
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exception = EXCP_AdES;
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} else {
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exception = EXCP_AdEL;
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@ -427,7 +427,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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break;
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
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if (rw == MMU_DATA_STORE) {
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if (access_type == MMU_DATA_STORE) {
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exception = EXCP_TLBS;
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} else {
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exception = EXCP_TLBL;
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@ -436,7 +436,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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break;
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case TLBRET_INVALID:
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/* TLB match with no valid bit */
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if (rw == MMU_DATA_STORE) {
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if (access_type == MMU_DATA_STORE) {
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exception = EXCP_TLBS;
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} else {
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exception = EXCP_TLBL;
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