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target/mips/translate: Simplify PCPYH using deposit_i64()

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Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-02-13 01:09:57 +01:00
parent f9fa53f197
commit ca8def9bdb
1 changed files with 4 additions and 30 deletions
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34
target/mips/translate.c
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@ -24091,36 +24091,10 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
tcg_gen_movi_i64(cpu_gpr[rd], 0);
tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
} else {
TCGv_i64 t0 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new();
uint64_t mask = (1ULL << 16) - 1;
tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
tcg_gen_movi_i64(t1, 0);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_mov_i64(cpu_gpr[rd], t1);
tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask);
tcg_gen_movi_i64(t1, 0);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_mov_i64(cpu_gpr_hi[rd], t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32);
tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt], 16, 16);
tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd], 32, 32);
}
}