hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35
Implement notifications and gpe to support q35 ACPI PCI hot-plug. Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20210713004205.775386-2-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>stable-6.1
Julia Suvorova
Michael S. Tsirkin
parent
bd306cfeee
commit
caf108bc58
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@ -37,7 +37,6 @@
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#include "qom/qom-qobject.h"
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#include "trace.h"
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#define ACPI_PCIHP_ADDR 0xae00
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#define ACPI_PCIHP_SIZE 0x0018
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#define PCI_UP_BASE 0x0000
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#define PCI_DOWN_BASE 0x0004
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@ -488,10 +487,11 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
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};
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void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
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MemoryRegion *address_space_io, bool bridges_enabled)
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MemoryRegion *address_space_io, bool bridges_enabled,
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uint16_t io_base)
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{
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s->io_len = ACPI_PCIHP_SIZE;
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s->io_base = ACPI_PCIHP_ADDR;
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s->io_base = io_base;
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s->root = root_bus;
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s->legacy_piix = !bridges_enabled;
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@ -49,6 +49,8 @@
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#define GPE_BASE 0xafe0
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#define GPE_LEN 4
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#define ACPI_PCIHP_ADDR_PIIX4 0xae00
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struct pci_status {
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uint32_t up; /* deprecated, maintained for migration compatibility */
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uint32_t down;
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@ -607,7 +609,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
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if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) {
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acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
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s->use_acpi_hotplug_bridge);
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s->use_acpi_hotplug_bridge, ACPI_PCIHP_ADDR_PIIX4);
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}
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s->cpu_hotplug_legacy = true;
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@ -219,10 +219,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
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/* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
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pm->fadt.rev = 1;
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pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
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pm->pcihp_io_base =
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object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
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pm->pcihp_io_len =
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object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
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}
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if (lpc) {
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uint64_t smi_features = object_property_get_uint(lpc,
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@ -238,6 +234,10 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
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pm->smi_on_cpu_unplug =
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!!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
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}
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pm->pcihp_io_base =
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object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
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pm->pcihp_io_len =
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object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
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/* The above need not be conditional on machine type because the reset port
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* happens to be the same on PIIX (pc) and ICH9 (q35). */
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@ -392,6 +392,9 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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if (!pdev) {
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if (bsel) { /* add hotplug slots for non present devices */
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if (pci_bus_is_express(bus) && slot > 0) {
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break;
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}
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dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
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aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
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aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
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@ -521,7 +524,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
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QLIST_FOREACH(sec, &bus->child, sibling) {
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int32_t devfn = sec->parent_dev->devfn;
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if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
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if (pci_bus_is_root(sec)) {
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continue;
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}
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@ -1251,7 +1254,7 @@ static void build_piix4_isa_bridge(Aml *table)
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aml_append(table, scope);
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}
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static void build_piix4_pci_hotplug(Aml *table)
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static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
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{
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Aml *scope;
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Aml *field;
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@ -1260,20 +1263,22 @@ static void build_piix4_pci_hotplug(Aml *table)
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scope = aml_scope("_SB.PCI0");
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aml_append(scope,
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aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
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aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
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field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
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aml_append(field, aml_named_field("PCIU", 32));
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aml_append(field, aml_named_field("PCID", 32));
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aml_append(scope, field);
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aml_append(scope,
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aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
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aml_operation_region("SEJ", AML_SYSTEM_IO,
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aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
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field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
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aml_append(field, aml_named_field("B0EJ", 32));
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aml_append(scope, field);
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aml_append(scope,
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aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08));
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aml_operation_region("BNMR", AML_SYSTEM_IO,
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aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
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field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
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aml_append(field, aml_named_field("BNUM", 32));
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aml_append(field, aml_named_field("PIDX", 32));
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@ -1407,7 +1412,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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build_piix4_isa_bridge(dsdt);
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build_isa_devices_aml(dsdt);
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if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
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build_piix4_pci_hotplug(dsdt);
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build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
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}
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build_piix4_pci0_int(dsdt);
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} else {
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@ -1455,6 +1460,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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}
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build_q35_isa_bridge(dsdt);
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build_isa_devices_aml(dsdt);
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if (pm->pcihp_bridge_en) {
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build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
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}
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build_q35_pci0_int(dsdt);
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if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
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build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
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@ -1489,7 +1497,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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{
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aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
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if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
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if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
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method = aml_method("_E01", 0, AML_NOTSERIALIZED);
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aml_append(method,
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aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
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@ -5,6 +5,10 @@
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extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio;
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/* PCI Hot-plug registers bases. See docs/spec/acpi_pci_hotplug.txt */
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#define ACPI_PCIHP_SEJ_BASE 0x8
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#define ACPI_PCIHP_BNMR_BASE 0x10
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void acpi_setup(void);
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#endif
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@ -28,6 +28,8 @@
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#include "hw/acpi/acpi_dev_interface.h"
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#include "hw/acpi/tco.h"
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#define ACPI_PCIHP_ADDR_ICH9 0x0cc4
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typedef struct ICH9LPCPMRegs {
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/*
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* In ich9 spec says that pm1_cnt register is 32bit width and
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@ -55,7 +55,8 @@ typedef struct AcpiPciHpState {
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} AcpiPciHpState;
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void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root,
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MemoryRegion *address_space_io, bool bridges_enabled);
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MemoryRegion *address_space_io, bool bridges_enabled,
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uint16_t io_base);
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void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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