target/riscv: Implement riscv_cpu_unassigned_access
This patch adds support for the riscv_cpu_unassigned_access call and will raise a load or store access fault. Signed-off-by: Michael Clark <mjc@sifive.com> [Changes by AF: - Squash two patches and rewrite commit message - Set baddr to the access address ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -482,6 +482,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
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cc->gdb_stop_before_watchpoint = true;
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cc->disas_set_info = riscv_cpu_disas_set_info;
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#ifndef CONFIG_USER_ONLY
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cc->do_unassigned_access = riscv_cpu_unassigned_access;
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cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
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cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
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#endif
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@ -259,6 +259,8 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
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bool is_exec, int unused, unsigned size);
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char *riscv_isa_string(RISCVCPU *cpu);
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void riscv_cpu_list(void);
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@ -375,6 +375,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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return phys_addr;
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}
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void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
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bool is_exec, int unused, unsigned size)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (is_write) {
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cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
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} else {
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cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
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}
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env->badaddr = addr;
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riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
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}
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void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr)
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