target/sh4: Introduce CHECK_SH4A
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-24-rth@twiddle.net> [aurel32: fix conflict] Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -389,6 +389,11 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
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goto do_illegal; \
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goto do_illegal; \
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}
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}
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#define CHECK_SH4A \
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if (!(ctx->features & SH_FEATURE_SH4A)) { \
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goto do_illegal; \
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}
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static void _decode_opc(DisasContext * ctx)
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static void _decode_opc(DisasContext * ctx)
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{
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{
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/* This code tries to make movcal emulation sufficiently
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/* This code tries to make movcal emulation sufficiently
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@ -1467,7 +1472,7 @@ static void _decode_opc(DisasContext * ctx)
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LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
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LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED)
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LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
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LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED)
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ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED)
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ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED)
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LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED if (!(ctx->features & SH_FEATURE_SH4A)) break;)
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LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED CHECK_SH4A)
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LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
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LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED)
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LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
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LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {})
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LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
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LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {})
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@ -1517,21 +1522,19 @@ static void _decode_opc(DisasContext * ctx)
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ctx->has_movcal = 1;
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ctx->has_movcal = 1;
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return;
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return;
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case 0x40a9: /* movua.l @Rm,R0 */
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case 0x40a9: /* movua.l @Rm,R0 */
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CHECK_SH4A
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/* Load non-boundary-aligned data */
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/* Load non-boundary-aligned data */
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if (ctx->features & SH_FEATURE_SH4A) {
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx,
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx,
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MO_TEUL | MO_UNALN);
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MO_TEUL | MO_UNALN);
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return;
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return;
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}
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break;
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break;
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case 0x40e9: /* movua.l @Rm+,R0 */
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case 0x40e9: /* movua.l @Rm+,R0 */
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CHECK_SH4A
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/* Load non-boundary-aligned data */
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/* Load non-boundary-aligned data */
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if (ctx->features & SH_FEATURE_SH4A) {
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx,
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx,
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MO_TEUL | MO_UNALN);
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MO_TEUL | MO_UNALN);
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tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
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tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
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return;
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return;
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}
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break;
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break;
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case 0x0029: /* movt Rn */
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case 0x0029: /* movt Rn */
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tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
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tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
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@ -1542,7 +1545,8 @@ static void _decode_opc(DisasContext * ctx)
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If (T == 1) R0 -> (Rn)
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If (T == 1) R0 -> (Rn)
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0 -> LDST
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0 -> LDST
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*/
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*/
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if (ctx->features & SH_FEATURE_SH4A) {
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CHECK_SH4A
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{
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TCGLabel *label = gen_new_label();
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TCGLabel *label = gen_new_label();
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tcg_gen_mov_i32(cpu_sr_t, cpu_ldst);
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tcg_gen_mov_i32(cpu_sr_t, cpu_ldst);
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tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
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tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
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@ -1550,8 +1554,7 @@ static void _decode_opc(DisasContext * ctx)
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gen_set_label(label);
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gen_set_label(label);
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tcg_gen_movi_i32(cpu_ldst, 0);
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tcg_gen_movi_i32(cpu_ldst, 0);
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return;
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return;
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} else
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}
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break;
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case 0x0063:
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case 0x0063:
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/* MOVLI.L @Rm,R0
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/* MOVLI.L @Rm,R0
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1 -> LDST
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1 -> LDST
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@ -1559,13 +1562,11 @@ static void _decode_opc(DisasContext * ctx)
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When interrupt/exception
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When interrupt/exception
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occurred 0 -> LDST
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occurred 0 -> LDST
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*/
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*/
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if (ctx->features & SH_FEATURE_SH4A) {
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CHECK_SH4A
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tcg_gen_movi_i32(cpu_ldst, 0);
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tcg_gen_movi_i32(cpu_ldst, 0);
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);
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tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);
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tcg_gen_movi_i32(cpu_ldst, 1);
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tcg_gen_movi_i32(cpu_ldst, 1);
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return;
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return;
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} else
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break;
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case 0x0093: /* ocbi @Rn */
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case 0x0093: /* ocbi @Rn */
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{
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{
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gen_helper_ocbi(cpu_env, REG(B11_8));
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gen_helper_ocbi(cpu_env, REG(B11_8));
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@ -1580,20 +1581,15 @@ static void _decode_opc(DisasContext * ctx)
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case 0x0083: /* pref @Rn */
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case 0x0083: /* pref @Rn */
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return;
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return;
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case 0x00d3: /* prefi @Rn */
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case 0x00d3: /* prefi @Rn */
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if (ctx->features & SH_FEATURE_SH4A)
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CHECK_SH4A
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return;
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return;
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else
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break;
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case 0x00e3: /* icbi @Rn */
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case 0x00e3: /* icbi @Rn */
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if (ctx->features & SH_FEATURE_SH4A)
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CHECK_SH4A
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return;
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return;
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else
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break;
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case 0x00ab: /* synco */
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case 0x00ab: /* synco */
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if (ctx->features & SH_FEATURE_SH4A) {
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CHECK_SH4A
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
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return;
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return;
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}
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break;
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break;
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case 0x4024: /* rotcl Rn */
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case 0x4024: /* rotcl Rn */
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{
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{
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