target/ppc: Add ibm,processor-radix-AP-encodings for TCG
The ibm,processor-radix-AP-encodings device tree property of the cpu node is used to specify the radix mode supported page sizes of the processor to the guest os. Contained in the top 3 bits of the msb is the actual page size (AP) encoding associated with the corresponding radix mode supported page size. Add this property for a TCG guest, note the TCG code is capable of translating any format so just add the 4 default page sizes. The ibm,processor-radix-AP-encodings device tree property is defined as: One to n cells in ascending order of radix mode supported page sizes encoded as BE ints (32bit on ppc) in the form: 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy - 0bxxx -> AP encoding - 0byyyyyyyyyyyyyyyyyyyyyyyyyyyyy -> supported page size encoded as a shift Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -8808,6 +8808,25 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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}
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#ifdef CONFIG_SOFTMMU
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/*
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* Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
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* Encoded as array of int_32s in the form:
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* 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
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* x -> AP encoding
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* y -> radix mode supported page size (encoded as a shift)
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*/
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static struct ppc_radix_page_info POWER9_radix_page_info = {
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.count = 4,
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.entries = {
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0x0000000c, /* 4K - enc: 0x0 */
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0xa0000010, /* 64K - enc: 0x5 */
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0x20000015, /* 2M - enc: 0x1 */
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0x4000001e /* 1G - enc: 0x2 */
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}
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};
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#endif /* CONFIG_SOFTMMU */
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static void init_proc_POWER9(CPUPPCState *env)
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{
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/* Common Registers */
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@ -8959,6 +8978,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
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pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
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/* segment page size remain the same */
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pcc->sps = &POWER7_POWER8_sps;
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pcc->radix_page_info = &POWER9_radix_page_info;
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER8;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
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