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target/arm: Implement SVE floating-point round to integral value

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180627043328.11531-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-06-29 15:11:10 +01:00 committed by Peter Maydell
parent df4de1affc
commit cda3c75322
4 changed files with 108 additions and 0 deletions
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14
target/arm/helper-sve.h
View file

@ -985,6 +985,20 @@ DEF_HELPER_FLAGS_5(sve_fcvtzu_sd, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve_fcvtzu_dd, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_frint_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_frint_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_frint_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_frintx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_frintx_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_frintx_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,

9
target/arm/sve.decode
View file

@ -845,6 +845,15 @@ FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
# SVE floating-point round to integral value
FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
# SVE integer convert to floating-point
SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0

8
target/arm/sve_helper.c
View file

@ -3290,6 +3290,14 @@ DO_ZPZ_FP(sve_fcvtzu_sd, uint64_t, , vfp_float32_to_uint64_rtz)
DO_ZPZ_FP(sve_fcvtzu_ds, uint64_t, , helper_vfp_touizd)
DO_ZPZ_FP(sve_fcvtzu_dd, uint64_t, , vfp_float64_to_uint64_rtz)
DO_ZPZ_FP(sve_frint_h, uint16_t, H1_2, helper_advsimd_rinth)
DO_ZPZ_FP(sve_frint_s, uint32_t, H1_4, helper_rints)
DO_ZPZ_FP(sve_frint_d, uint64_t, , helper_rintd)
DO_ZPZ_FP(sve_frintx_h, uint16_t, H1_2, float16_round_to_int)
DO_ZPZ_FP(sve_frintx_s, uint32_t, H1_4, float32_round_to_int)
DO_ZPZ_FP(sve_frintx_d, uint64_t, , float64_round_to_int)
DO_ZPZ_FP(sve_scvt_hh, uint16_t, H1_2, int16_to_float16)
DO_ZPZ_FP(sve_scvt_sh, uint32_t, H1_4, int32_to_float16)
DO_ZPZ_FP(sve_scvt_ss, uint32_t, H1_4, int32_to_float32)

77
target/arm/translate-sve.c
View file

@ -4040,6 +4040,83 @@ static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
}
static gen_helper_gvec_3_ptr * const frint_fns[3] = {
gen_helper_sve_frint_h,
gen_helper_sve_frint_s,
gen_helper_sve_frint_d
};
static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
if (a->esz == 0) {
return false;
}
return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
frint_fns[a->esz - 1]);
}
static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
static gen_helper_gvec_3_ptr * const fns[3] = {
gen_helper_sve_frintx_h,
gen_helper_sve_frintx_s,
gen_helper_sve_frintx_d
};
if (a->esz == 0) {
return false;
}
return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
}
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)
{
if (a->esz == 0) {
return false;
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
TCGv_i32 tmode = tcg_const_i32(mode);
TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16);
gen_helper_set_rmode(tmode, tmode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, frint_fns[a->esz - 1]);
gen_helper_set_rmode(tmode, tmode, status);
tcg_temp_free_i32(tmode);
tcg_temp_free_ptr(status);
}
return true;
}
static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_frint_mode(s, a, float_round_nearest_even);
}
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_frint_mode(s, a, float_round_up);
}
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_frint_mode(s, a, float_round_down);
}
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_frint_mode(s, a, float_round_to_zero);
}
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_frint_mode(s, a, float_round_ties_away);
}
static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);