intel_iommu: refine SL-PEs reserved fields checking
1. split the resevred fields arrays into two ones, 2. large page only effect for L2(2M) and L3(1G), so remove checking of L1 and L4 for large page. Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> Signed-off-by: Qi, Yadong <yadong.qi@intel.com> Message-Id: <20191125003321.5669-2-yadong.qi@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -910,19 +910,23 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
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/*
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/*
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* Rsvd field masks for spte:
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* Rsvd field masks for spte:
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* Index [1] to [4] 4k pages
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* vtd_spte_rsvd 4k pages
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* Index [5] to [8] large pages
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* vtd_spte_rsvd_large large pages
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*/
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*/
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static uint64_t vtd_paging_entry_rsvd_field[9];
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static uint64_t vtd_spte_rsvd[5];
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static uint64_t vtd_spte_rsvd_large[5];
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static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
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static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
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{
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{
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if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
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uint64_t rsvd_mask = vtd_spte_rsvd[level];
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/* Maybe large page */
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return slpte & vtd_paging_entry_rsvd_field[level + 4];
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if ((level == VTD_SL_PD_LEVEL || level == VTD_SL_PDP_LEVEL) &&
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} else {
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(slpte & VTD_SL_PT_PAGE_SIZE_MASK)) {
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return slpte & vtd_paging_entry_rsvd_field[level];
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/* large page */
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rsvd_mask = vtd_spte_rsvd_large[level];
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}
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}
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return slpte & rsvd_mask;
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}
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}
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/* Find the VTD address space associated with a given bus number */
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/* Find the VTD address space associated with a given bus number */
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@ -3549,15 +3553,14 @@ static void vtd_init(IntelIOMMUState *s)
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/*
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/*
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* Rsvd field masks for spte
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* Rsvd field masks for spte
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*/
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*/
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vtd_paging_entry_rsvd_field[0] = ~0ULL;
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vtd_spte_rsvd[0] = ~0ULL;
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vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
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vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
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if (x86_iommu_ir_supported(x86_iommu)) {
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if (x86_iommu_ir_supported(x86_iommu)) {
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s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
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s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
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@ -395,14 +395,11 @@ typedef union VTDInvDesc VTDInvDesc;
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
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#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
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(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
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(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
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#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
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(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
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#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
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(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
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(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
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/* Information about page-selective IOTLB invalidate */
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/* Information about page-selective IOTLB invalidate */
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struct VTDIOTLBPageInvInfo {
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struct VTDIOTLBPageInvInfo {
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