q35: Use type-safe cast instead of direct access of parent dev
And remove variables if possible. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> [AF: Converted remaining access and renamed to parent_obj] Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -60,6 +60,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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const char *boot_device = args->boot_device;
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ram_addr_t below_4g_mem_size, above_4g_mem_size;
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Q35PCIHost *q35_host;
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PCIHostState *phb;
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PCIBus *host_bus;
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PCIDevice *lpc;
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BusState *idebus[MAX_SATA_PORTS];
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@ -139,7 +140,8 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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q35_host->mch.guest_info = guest_info;
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/* pci */
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qdev_init_nofail(DEVICE(q35_host));
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host_bus = q35_host->host.pci.bus;
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phb = PCI_HOST_BRIDGE(q35_host);
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host_bus = phb->bus;
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/* create ISA bus */
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lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
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ICH9_LPC_FUNC), true,
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@ -36,28 +36,26 @@
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static int q35_host_init(SysBusDevice *dev)
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{
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PCIBus *b;
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PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
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Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
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PCIHostState *pci = PCI_HOST_BRIDGE(dev);
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Q35PCIHost *s = Q35_HOST_DEVICE(dev);
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memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci,
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"pci-conf-idx", 4);
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sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
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sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
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sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
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memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci,
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"pci-conf-data", 4);
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sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
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sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
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sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
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if (pcie_host_init(&s->host) < 0) {
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if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
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return -1;
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}
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b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
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pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
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s->mch.pci_address_space, s->mch.address_space_io,
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0, TYPE_PCIE_BUS);
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s->host.pci.bus = b;
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qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
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qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
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qdev_init_nofail(DEVICE(&s->mch));
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return 0;
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@ -71,7 +69,7 @@ static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
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}
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static Property mch_props[] = {
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DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
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DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -113,10 +111,9 @@ static const TypeInfo q35_host_info = {
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/* PCIe MMCFG */
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static void mch_update_pciexbar(MCHPCIState *mch)
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{
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PCIDevice *pci_dev = &mch->d;
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BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
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DeviceState *qdev = bus->parent;
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Q35PCIHost *s = Q35_HOST_DEVICE(qdev);
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PCIDevice *pci_dev = PCI_DEVICE(mch);
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BusState *bus = qdev_get_parent_bus(DEVICE(mch));
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PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
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uint64_t pciexbar;
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int enable;
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@ -148,18 +145,19 @@ static void mch_update_pciexbar(MCHPCIState *mch)
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break;
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}
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addr = pciexbar & addr_mask;
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pcie_host_mmcfg_update(&s->host, enable, addr, length);
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pcie_host_mmcfg_update(pehb, enable, addr, length);
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}
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/* PAM */
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static void mch_update_pam(MCHPCIState *mch)
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{
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PCIDevice *pd = PCI_DEVICE(mch);
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int i;
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memory_region_transaction_begin();
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for (i = 0; i < 13; i++) {
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pam_update(&mch->pam_regions[i], i,
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mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
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pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
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}
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memory_region_transaction_commit();
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}
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@ -167,8 +165,10 @@ static void mch_update_pam(MCHPCIState *mch)
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/* SMRAM */
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static void mch_update_smram(MCHPCIState *mch)
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{
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PCIDevice *pd = PCI_DEVICE(mch);
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memory_region_transaction_begin();
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smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
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smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
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mch->smm_enabled);
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memory_region_transaction_commit();
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}
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@ -176,9 +176,10 @@ static void mch_update_smram(MCHPCIState *mch)
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static void mch_set_smm(int smm, void *arg)
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{
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MCHPCIState *mch = arg;
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PCIDevice *pd = PCI_DEVICE(mch);
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memory_region_transaction_begin();
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smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
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smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
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&mch->smram_region);
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memory_region_transaction_commit();
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}
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@ -228,7 +229,7 @@ static const VMStateDescription vmstate_mch = {
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.minimum_version_id_old = 1,
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.post_load = mch_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(d, MCHPCIState),
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VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
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VMSTATE_UINT8(smm_enabled, MCHPCIState),
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VMSTATE_END_OF_LIST()
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}
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@ -43,7 +43,10 @@
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OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
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typedef struct MCHPCIState {
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PCIDevice d;
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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MemoryRegion *ram_memory;
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MemoryRegion *pci_address_space;
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MemoryRegion *system_memory;
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@ -59,7 +62,10 @@ typedef struct MCHPCIState {
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} MCHPCIState;
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typedef struct Q35PCIHost {
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PCIExpressHost host;
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/*< private >*/
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PCIExpressHost parent_obj;
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/*< public >*/
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MCHPCIState mch;
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} Q35PCIHost;
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