target-ppc: support KVM_CAP_PPC_MMU_RADIX, KVM_CAP_PPC_MMU_HASH_V3
Query and cache the value of two new KVM capabilities that indicate KVM's support for new radix and hash modes of the MMU. Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -86,6 +86,8 @@ static int cap_papr;
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static int cap_htab_fd;
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static int cap_fixup_hcalls;
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static int cap_htm; /* Hardware transactional memory support */
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static int cap_mmu_radix;
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static int cap_mmu_hash_v3;
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static uint32_t debug_inst_opcode;
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@ -140,6 +142,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
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cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
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cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
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cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
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cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
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cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
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if (!cap_interrupt_level) {
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fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
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@ -2354,6 +2358,16 @@ bool kvmppc_has_cap_htm(void)
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return cap_htm;
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}
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bool kvmppc_has_cap_mmu_radix(void)
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{
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return cap_mmu_radix;
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}
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bool kvmppc_has_cap_mmu_hash_v3(void)
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{
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return cap_mmu_hash_v3;
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}
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static PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
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{
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ObjectClass *oc = OBJECT_CLASS(pcc);
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@ -54,6 +54,8 @@ void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n);
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void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1);
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bool kvmppc_has_cap_fixup_hcalls(void);
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bool kvmppc_has_cap_htm(void);
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bool kvmppc_has_cap_mmu_radix(void);
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bool kvmppc_has_cap_mmu_hash_v3(void);
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int kvmppc_enable_hwrng(void);
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int kvmppc_put_books_sregs(PowerPCCPU *cpu);
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PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void);
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@ -254,6 +256,16 @@ static inline bool kvmppc_has_cap_htm(void)
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return false;
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}
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static inline bool kvmppc_has_cap_mmu_radix(void)
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{
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return false;
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}
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static inline bool kvmppc_has_cap_mmu_hash_v3(void)
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{
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return false;
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}
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static inline int kvmppc_enable_hwrng(void)
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{
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return -1;
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