hw/arm/sysbus-fdt: enable amd-xgbe dynamic instantiation
This patch allows the instantiation of the vfio-amd-xgbe device from the QEMU command line (-device vfio-amd-xgbe,host="<device>"). The guest is exposed with a device tree node that combines the description of both XGBE and PHY (representation supported from 4.2 onwards kernel): Documentation/devicetree/bindings/net/amd-xgbe.txt. There are 5 register regions, 6 interrupts including 4 optional edge-sensitive per-channel interrupts. Some property values are inherited from host device tree. Host device tree must feature a combined XGBE/PHY representation (>= 4.2 host kernel). 2 clock nodes (dma and ptp) also are created. It is checked those clocks are fixed on host side. AMD XGBE node creation function has a dependency on vfio Linux header and more generally node creation function for VFIO platform devices only make sense with CONFIG_LINUX so let's protect this code with #ifdef CONFIG_LINUX. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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@ -23,6 +23,10 @@
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#include "qemu/osdep.h"
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#include <libfdt.h>
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#include "qemu-common.h"
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#ifdef CONFIG_LINUX
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#include <linux/vfio.h>
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#endif
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#include "hw/arm/sysbus-fdt.h"
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#include "qemu/error-report.h"
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#include "sysemu/device_tree.h"
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@ -30,6 +34,7 @@
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#include "sysemu/sysemu.h"
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#include "hw/vfio/vfio-platform.h"
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#include "hw/vfio/vfio-calxeda-xgmac.h"
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#include "hw/vfio/vfio-amd-xgbe.h"
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#include "hw/arm/fdt.h"
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/*
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@ -65,6 +70,8 @@ typedef struct HostProperty {
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bool optional;
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} HostProperty;
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#ifdef CONFIG_LINUX
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/**
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* copy_properties_from_host
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*
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@ -127,12 +134,9 @@ static HostProperty clock_copied_properties[] = {
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* @host_phandle: phandle of the clock in host device tree
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* @guest_phandle: phandle to assign to the guest node
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*/
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void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
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uint32_t host_phandle,
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uint32_t guest_phandle);
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void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
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uint32_t host_phandle,
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uint32_t guest_phandle)
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static void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
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uint32_t host_phandle,
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uint32_t guest_phandle)
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{
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char *node_path = NULL;
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char *nodename;
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@ -177,6 +181,28 @@ void fdt_build_clock_node(void *host_fdt, void *guest_fdt,
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g_free(node_path);
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}
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/**
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* sysfs_to_dt_name: convert the name found in sysfs into the node name
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* for instance e0900000.xgmac is converted into xgmac@e0900000
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* @sysfs_name: directory name in sysfs
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*
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* returns the device tree name upon success or NULL in case the sysfs name
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* does not match the expected format
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*/
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static char *sysfs_to_dt_name(const char *sysfs_name)
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{
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gchar **substrings = g_strsplit(sysfs_name, ".", 2);
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char *dt_name = NULL;
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if (!substrings || !substrings[0] || !substrings[1]) {
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goto out;
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}
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dt_name = g_strdup_printf("%s@%s", substrings[1], substrings[0]);
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out:
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g_strfreev(substrings);
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return dt_name;
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}
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/* Device Specific Code */
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/**
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@ -244,9 +270,165 @@ fail_reg:
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return ret;
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}
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/* AMD xgbe properties whose values are copied/pasted from host */
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static HostProperty amd_xgbe_copied_properties[] = {
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{"compatible", false},
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{"dma-coherent", true},
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{"amd,per-channel-interrupt", true},
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{"phy-mode", false},
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{"mac-address", true},
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{"amd,speed-set", false},
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{"amd,serdes-blwc", true},
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{"amd,serdes-cdr-rate", true},
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{"amd,serdes-pq-skew", true},
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{"amd,serdes-tx-amp", true},
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{"amd,serdes-dfe-tap-config", true},
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{"amd,serdes-dfe-tap-enable", true},
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{"clock-names", false},
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};
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/**
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* add_amd_xgbe_fdt_node
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*
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* Generates the combined xgbe/phy node following kernel >=4.2
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* binding documentation:
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* Documentation/devicetree/bindings/net/amd-xgbe.txt:
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* Also 2 clock nodes are created (dma and ptp)
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*
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* Asserts in case of error
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*/
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static int add_amd_xgbe_fdt_node(SysBusDevice *sbdev, void *opaque)
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{
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PlatformBusFDTData *data = opaque;
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PlatformBusDevice *pbus = data->pbus;
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VFIOPlatformDevice *vdev = VFIO_PLATFORM_DEVICE(sbdev);
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VFIODevice *vbasedev = &vdev->vbasedev;
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VFIOINTp *intp;
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const char *parent_node = data->pbus_node_name;
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char **node_path, *nodename, *dt_name;
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void *guest_fdt = data->fdt, *host_fdt;
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const void *r;
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int i, prop_len;
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uint32_t *irq_attr, *reg_attr, *host_clock_phandles;
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uint64_t mmio_base, irq_number;
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uint32_t guest_clock_phandles[2];
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host_fdt = load_device_tree_from_sysfs();
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dt_name = sysfs_to_dt_name(vbasedev->name);
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if (!dt_name) {
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error_setg(&error_fatal, "%s incorrect sysfs device name %s",
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__func__, vbasedev->name);
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}
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node_path = qemu_fdt_node_path(host_fdt, dt_name, vdev->compat,
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&error_fatal);
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if (!node_path || !node_path[0]) {
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error_setg(&error_fatal, "%s unable to retrieve node path for %s/%s",
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__func__, dt_name, vdev->compat);
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}
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if (node_path[1]) {
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error_setg(&error_fatal, "%s more than one node matching %s/%s!",
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__func__, dt_name, vdev->compat);
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}
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g_free(dt_name);
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if (vbasedev->num_regions != 5) {
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error_setg(&error_fatal, "%s Does the host dt node combine XGBE/PHY?",
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__func__);
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}
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/* generate nodes for DMA_CLK and PTP_CLK */
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r = qemu_fdt_getprop(host_fdt, node_path[0], "clocks",
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&prop_len, &error_fatal);
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if (prop_len != 8) {
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error_setg(&error_fatal, "%s clocks property should contain 2 handles",
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__func__);
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}
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host_clock_phandles = (uint32_t *)r;
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guest_clock_phandles[0] = qemu_fdt_alloc_phandle(guest_fdt);
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guest_clock_phandles[1] = qemu_fdt_alloc_phandle(guest_fdt);
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/**
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* clock handles fetched from host dt are in be32 layout whereas
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* rest of the code uses cpu layout. Also guest clock handles are
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* in cpu layout.
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*/
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fdt_build_clock_node(host_fdt, guest_fdt,
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be32_to_cpu(host_clock_phandles[0]),
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guest_clock_phandles[0]);
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fdt_build_clock_node(host_fdt, guest_fdt,
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be32_to_cpu(host_clock_phandles[1]),
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guest_clock_phandles[1]);
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/* combined XGBE/PHY node */
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mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
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nodename = g_strdup_printf("%s/%s@%" PRIx64, parent_node,
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vbasedev->name, mmio_base);
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qemu_fdt_add_subnode(guest_fdt, nodename);
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copy_properties_from_host(amd_xgbe_copied_properties,
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ARRAY_SIZE(amd_xgbe_copied_properties),
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host_fdt, guest_fdt,
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node_path[0], nodename);
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qemu_fdt_setprop_cells(guest_fdt, nodename, "clocks",
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guest_clock_phandles[0],
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guest_clock_phandles[1]);
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reg_attr = g_new(uint32_t, vbasedev->num_regions * 2);
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for (i = 0; i < vbasedev->num_regions; i++) {
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mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i);
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reg_attr[2 * i] = cpu_to_be32(mmio_base);
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reg_attr[2 * i + 1] = cpu_to_be32(
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memory_region_size(&vdev->regions[i]->mem));
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}
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qemu_fdt_setprop(guest_fdt, nodename, "reg", reg_attr,
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vbasedev->num_regions * 2 * sizeof(uint32_t));
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irq_attr = g_new(uint32_t, vbasedev->num_irqs * 3);
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for (i = 0; i < vbasedev->num_irqs; i++) {
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irq_number = platform_bus_get_irqn(pbus, sbdev , i)
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+ data->irq_start;
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irq_attr[3 * i] = cpu_to_be32(GIC_FDT_IRQ_TYPE_SPI);
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irq_attr[3 * i + 1] = cpu_to_be32(irq_number);
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/*
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* General device interrupt and PCS auto-negotiation interrupts are
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* level-sensitive while the 4 per-channel interrupts are edge
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* sensitive
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*/
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QLIST_FOREACH(intp, &vdev->intp_list, next) {
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if (intp->pin == i) {
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break;
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}
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}
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if (intp->flags & VFIO_IRQ_INFO_AUTOMASKED) {
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irq_attr[3 * i + 2] = cpu_to_be32(GIC_FDT_IRQ_FLAGS_LEVEL_HI);
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} else {
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irq_attr[3 * i + 2] = cpu_to_be32(GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
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}
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}
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qemu_fdt_setprop(guest_fdt, nodename, "interrupts",
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irq_attr, vbasedev->num_irqs * 3 * sizeof(uint32_t));
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g_free(host_fdt);
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g_strfreev(node_path);
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g_free(irq_attr);
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g_free(reg_attr);
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g_free(nodename);
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return 0;
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}
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#endif /* CONFIG_LINUX */
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/* list of supported dynamic sysbus devices */
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static const NodeCreationPair add_fdt_node_functions[] = {
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#ifdef CONFIG_LINUX
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{TYPE_VFIO_CALXEDA_XGMAC, add_calxeda_midway_xgmac_fdt_node},
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{TYPE_VFIO_AMD_XGBE, add_amd_xgbe_fdt_node},
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#endif
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{"", NULL}, /* last element */
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};
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