target/arm: Perform per-insn cross-page check only for Thumb
ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -11888,6 +11888,13 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,
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max_insns = 1;
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}
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/* ARM is a fixed-length ISA. Bound the number of insns to execute
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to those left on the page. */
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if (!dc->thumb) {
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int bound = (dc->next_page_start - dc->base.pc_first) / 4;
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max_insns = MIN(max_insns, bound);
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}
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cpu_F0s = tcg_temp_new_i32();
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cpu_F1s = tcg_temp_new_i32();
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cpu_F0d = tcg_temp_new_i64();
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@ -12015,34 +12022,12 @@ static bool arm_pre_translate_insn(DisasContext *dc)
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return false;
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}
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static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc)
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static void arm_post_translate_insn(DisasContext *dc)
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{
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if (dc->condjmp && !dc->base.is_jmp) {
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gen_set_label(dc->condlabel);
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dc->condjmp = 0;
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}
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/* Translation stops when a conditional branch is encountered.
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* Otherwise the subsequent code could get translated several times.
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* Also stop translation when a page boundary is reached. This
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* ensures prefetch aborts occur at the right place.
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*
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* We want to stop the TB if the next insn starts in a new page,
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* or if it spans between this page and the next. This means that
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* if we're looking at the last halfword in the page we need to
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* see if it's a 16-bit Thumb insn (which will fit in this TB)
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* or a 32-bit Thumb insn (which won't).
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* This is to avoid generating a silly TB with a single 16-bit insn
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* in it at the end of this page (which would execute correctly
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* but isn't very efficient).
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*/
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if (dc->base.is_jmp == DISAS_NEXT
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&& (dc->pc >= dc->next_page_start
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|| (dc->pc >= dc->next_page_start - 3
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&& insn_crosses_page(env, dc)))) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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dc->base.pc_next = dc->pc;
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translator_loop_temp_check(&dc->base);
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}
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@ -12061,7 +12046,10 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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dc->pc += 4;
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disas_arm_insn(dc, insn);
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arm_post_translate_insn(env, dc);
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arm_post_translate_insn(dc);
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/* ARM is a fixed-length ISA. We performed the cross-page check
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in init_disas_context by adjusting max_insns. */
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}
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static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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@ -12085,7 +12073,27 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
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}
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}
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arm_post_translate_insn(env, dc);
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arm_post_translate_insn(dc);
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/* Thumb is a variable-length ISA. Stop translation when the next insn
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* will touch a new page. This ensures that prefetch aborts occur at
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* the right place.
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*
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* We want to stop the TB if the next insn starts in a new page,
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* or if it spans between this page and the next. This means that
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* if we're looking at the last halfword in the page we need to
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* see if it's a 16-bit Thumb insn (which will fit in this TB)
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* or a 32-bit Thumb insn (which won't).
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* This is to avoid generating a silly TB with a single 16-bit insn
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* in it at the end of this page (which would execute correctly
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* but isn't very efficient).
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*/
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if (dc->base.is_jmp == DISAS_NEXT
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&& (dc->pc >= dc->next_page_start
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|| (dc->pc >= dc->next_page_start - 3
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&& insn_crosses_page(env, dc)))) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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}
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}
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static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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