target/ppc: Add support for Radix partition-scoped translation
The Radix tree translation model currently supports process-scoped translation for the PowerNV machine (Hypervisor mode) and for the pSeries machine (Guest mode). Guests running under an emulated Hypervisor (PowerNV machine) require a new type of Radix translation, called partition-scoped, which is missing today. The Radix tree translation is a 2 steps process. The first step, process-scoped translation, converts an effective Address to a guest real address, and the second step, partition-scoped translation, converts a guest real address to a host real address. There are difference cases to covers : * Hypervisor real mode access: no Radix translation. * Hypervisor or host application access (quadrant 0 and 3) with relocation on: process-scoped translation. * Guest OS real mode access: only partition-scoped translation. * Guest OS real or guest application access (quadrant 0 and 3) with relocation on: both process-scoped translation and partition-scoped translations. * Hypervisor access in quadrant 1 and 2 with relocation on: both process-scoped translation and partition-scoped translations. The radix tree partition-scoped translation is performed using tables pointed to by the first double-word of the Partition Table Entries and process-scoped translation uses tables pointed to by the Process Table Entries (second double-word of the Partition Table Entries). Both partition-scoped and process-scoped translations process are identical and thus the radix tree traversing code is largely reused. However, errors in partition-scoped translations generate hypervisor exceptions. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200403140056.59465-5-clg@kaod.org> [dwg: Fixup from Greg Kurz folded in] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -463,6 +463,9 @@ typedef struct ppc_v3_pate_t {
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#define DSISR_AMR 0x00200000
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/* Unsupported Radix Tree Configuration */
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#define DSISR_R_BADCONFIG 0x00080000
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#define DSISR_ATOMIC_RC 0x00040000
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/* Unable to translate address of (guest) pde or process/page table entry */
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#define DSISR_PRTABLE_FAULT 0x00020000
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/* SRR1 error code fields */
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@ -506,9 +506,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
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case POWERPC_EXCP_ISEG: /* Instruction segment exception */
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case POWERPC_EXCP_TRACE: /* Trace exception */
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break;
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case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
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msr |= env->error_code;
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case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
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case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
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case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
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case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
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case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
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case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
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@ -103,6 +103,27 @@ static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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}
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}
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static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr,
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hwaddr g_raddr, uint32_t cause)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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if (rwx == 2) { /* H Instruction Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_HISI;
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env->spr[SPR_ASDR] = g_raddr;
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env->error_code = cause;
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} else { /* H Data Storage Interrupt */
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cs->exception_index = POWERPC_EXCP_HDSI;
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if (rwx == 1) { /* Write -> Store */
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cause |= DSISR_ISSTORE;
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}
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env->spr[SPR_HDSISR] = cause;
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env->spr[SPR_HDAR] = eaddr;
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env->spr[SPR_ASDR] = g_raddr;
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env->error_code = 0;
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}
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}
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static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte,
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int *fault_cause, int *prot,
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@ -243,6 +264,37 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
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return true;
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}
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static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx,
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vaddr eaddr, hwaddr g_raddr,
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ppc_v3_pate_t pate,
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hwaddr *h_raddr, int *h_prot,
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int *h_page_size, bool pde_addr,
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bool cause_excp)
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{
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int fault_cause = 0;
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hwaddr pte_addr;
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uint64_t pte;
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*h_page_size = PRTBE_R_GET_RTS(pate.dw0);
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/* No valid pte or access denied due to protection */
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if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RPDB,
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pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_size,
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&pte, &fault_cause, &pte_addr) ||
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ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true)) {
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if (pde_addr) /* address being translated was that of a guest pde */
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fault_cause |= DSISR_PRTABLE_FAULT;
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if (cause_excp) {
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ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause);
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}
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return 1;
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}
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/* Update Reference and Change Bits */
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot);
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return 0;
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}
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static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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vaddr eaddr, uint64_t pid,
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ppc_v3_pate_t pate, hwaddr *g_raddr,
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@ -250,9 +302,10 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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bool cause_excp)
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{
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CPUState *cs = CPU(cpu);
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uint64_t offset, size, prtbe_addr, prtbe0, pte;
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int fault_cause = 0;
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hwaddr pte_addr;
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CPUPPCState *env = &cpu->env;
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uint64_t offset, size, prtbe_addr, prtbe0, base_addr, nls, index, pte;
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int fault_cause = 0, h_page_size, h_prot;
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hwaddr h_raddr, pte_addr;
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int ret;
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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@ -266,18 +319,85 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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return 1;
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}
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prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset;
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prtbe0 = ldq_phys(cs->as, prtbe_addr);
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if (cpu->vhyp) {
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prtbe0 = ldq_phys(cs->as, prtbe_addr);
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} else {
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/*
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* Process table addresses are subject to partition-scoped
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* translation
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*
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* On a Radix host, the partition-scoped page table for LPID=0
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* is only used to translate the effective addresses of the
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* process table entries.
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*/
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ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, prtbe_addr,
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pate, &h_raddr, &h_prot,
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&h_page_size, 1, 1);
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if (ret) {
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return ret;
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}
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prtbe0 = ldq_phys(cs->as, h_raddr);
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}
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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*g_page_size = PRTBE_R_GET_RTS(prtbe0);
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ret = ppc_radix64_walk_tree(cs->as, eaddr & R_EADDR_MASK,
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prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
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g_raddr, g_page_size, &pte, &fault_cause,
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&pte_addr);
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base_addr = prtbe0 & PRTBE_R_RPDB;
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nls = prtbe0 & PRTBE_R_RPDS;
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if (msr_hv || cpu->vhyp) {
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/*
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* Can treat process table addresses as real addresses
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*/
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ret = ppc_radix64_walk_tree(cs->as, eaddr & R_EADDR_MASK, base_addr,
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nls, g_raddr, g_page_size, &pte,
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&fault_cause, &pte_addr);
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if (ret) {
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/* No valid PTE */
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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return ret;
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}
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} else {
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uint64_t rpn, mask;
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if (ret ||
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ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) {
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/* No valid pte or access denied due to protection */
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index = (eaddr & R_EADDR_MASK) >> (*g_page_size - nls); /* Shift */
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index &= ((1UL << nls) - 1); /* Mask */
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pte_addr = base_addr + (index * sizeof(pte));
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/*
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* Each process table address is subject to a partition-scoped
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* translation
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*/
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do {
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ret = ppc_radix64_partition_scoped_xlate(cpu, 0, eaddr, pte_addr,
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pate, &h_raddr, &h_prot,
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&h_page_size, 1, 1);
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if (ret) {
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return ret;
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}
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ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK, &h_raddr,
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&nls, g_page_size, &pte, &fault_cause);
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if (ret) {
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/* No valid pte */
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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return ret;
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}
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pte_addr = h_raddr;
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} while (!(pte & R_PTE_LEAF));
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rpn = pte & R_PTE_RPN;
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mask = (1UL << *g_page_size) - 1;
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/* Or high bits of rpn and low bits to ea to form whole real addr */
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*g_raddr = (rpn & ~mask) | (eaddr & mask);
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}
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if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)) {
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/* Access denied due to protection */
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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@ -289,11 +409,29 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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return 0;
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}
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/*
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* Radix tree translation is a 2 steps translation process:
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*
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* 1. Process-scoped translation: Guest Eff Addr -> Guest Real Addr
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* 2. Partition-scoped translation: Guest Real Addr -> Host Real Addr
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*
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* MSR[HV]
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* +-------------+----------------+---------------+
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* | | HV = 0 | HV = 1 |
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* +-------------+----------------+---------------+
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* | Relocation | Partition | No |
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* | = Off | Scoped | Translation |
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* Relocation +-------------+----------------+---------------+
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* | Relocation | Partition & | Process |
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* | = On | Process Scoped | Scoped |
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* +-------------+----------------+---------------+
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*/
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static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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bool relocation,
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hwaddr *raddr, int *psizep, int *protp,
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bool cause_excp)
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{
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CPUPPCState *env = &cpu->env;
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uint64_t lpid = 0, pid = 0;
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ppc_v3_pate_t pate;
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int psize, prot;
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@ -325,11 +463,6 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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}
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return 1;
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}
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/* We don't support guest mode yet */
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if (lpid != 0) {
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error_report("PowerNV guest support Unimplemented");
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exit(1);
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}
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}
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*psizep = INT_MAX;
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@ -340,6 +473,8 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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*
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* - Translates an effective address to a host real address in
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* quadrants 0 and 3 when HV=1.
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*
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* - Translates an effective address to a guest real address.
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*/
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if (relocation) {
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int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid,
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@ -354,7 +489,30 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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g_raddr = eaddr & R_EADDR_MASK;
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}
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*raddr = g_raddr;
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if (cpu->vhyp) {
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*raddr = g_raddr;
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} else {
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/*
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* Perform partition-scoped translation if !HV or HV access to
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* quadrants 1 or 2. Translates a guest real address to a host
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* real address.
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*/
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if (lpid || !msr_hv) {
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int ret;
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ret = ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_raddr,
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pate, raddr, &prot, &psize,
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0, cause_excp);
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if (ret) {
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return ret;
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}
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*psizep = MIN(*psizep, psize);
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*protp &= prot;
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} else {
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*raddr = g_raddr;
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}
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}
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return 0;
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}
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