target/ppc: Consolidate 64-bit server processor detection in a helper
We use PPC_SEGMENT_64B in various places to guard code that is specific to 64-bit server processors compliant with arch 2.x. Consolidate the logic in a helper macro with an explicit name. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <155327783157.1283071.3747129891004927299.stgit@bahia.lan> Tested-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1101,7 +1101,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
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tb_env = g_malloc0(sizeof(ppc_tb_t));
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env->tb_env = tb_env;
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tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
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if (env->insns_flags & PPC_SEGMENT_64B) {
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if (is_book3s_arch2x(env)) {
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/* All Book3S 64bit CPUs implement level based DEC logic */
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tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
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}
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@ -2409,6 +2409,12 @@ enum {
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target_ulong cpu_read_xer(CPUPPCState *env);
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void cpu_write_xer(CPUPPCState *env, target_ulong xer);
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/*
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* All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
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* have PPC_SEGMENT_64B.
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*/
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#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
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static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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{
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@ -152,7 +152,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
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* - 64-bit embedded implementations do not need any operation to be
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* performed when PR is set.
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*/
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if ((env->insns_flags & PPC_SEGMENT_64B) && ((value >> MSR_PR) & 1)) {
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if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
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value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
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}
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#endif
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@ -3755,7 +3755,7 @@ static void gen_bcond(DisasContext *ctx, int type)
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* arch 2.x, do implement a "test and decrement" logic instead,
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* as described in their respective UMs.
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*/
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if (unlikely(!(ctx->insns_flags & PPC_SEGMENT_64B))) {
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if (unlikely(!is_book3s_arch2x(ctx))) {
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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tcg_temp_free(temp);
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tcg_temp_free(target);
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@ -3913,7 +3913,7 @@ static void gen_rfi(DisasContext *ctx)
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/* This instruction doesn't exist anymore on 64-bit server
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* processors compliant with arch 2.x
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*/
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if (ctx->insns_flags & PPC_SEGMENT_64B) {
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if (is_book3s_arch2x(ctx)) {
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gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
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return;
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}
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@ -6535,8 +6535,7 @@ static void gen_msgclr(DisasContext *ctx)
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GEN_PRIV;
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#else
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CHK_HV;
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/* 64-bit server processors compliant with arch 2.x */
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if (ctx->insns_flags & PPC_SEGMENT_64B) {
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if (is_book3s_arch2x(ctx)) {
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gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
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} else {
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gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
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@ -6550,8 +6549,7 @@ static void gen_msgsnd(DisasContext *ctx)
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GEN_PRIV;
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#else
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CHK_HV;
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/* 64-bit server processors compliant with arch 2.x */
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if (ctx->insns_flags & PPC_SEGMENT_64B) {
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if (is_book3s_arch2x(ctx)) {
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gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
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} else {
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gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
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