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MIPS queue for QEMU 3.1-rc2 - v2

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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-november-2018-v2' into staging

MIPS queue for QEMU 3.1-rc2 - v2

# gpg: Signature made Sat 17 Nov 2018 18:30:46 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-november-2018-v2:
  MAINTAINERS: Add Stefan Markovic as a MIPS reviewer
  target/mips: Disable R5900 support
  target/mips: Rename MMI-related functions
  target/mips: Rename MMI-related opcodes
  target/mips: Rename MMI-related masks
  target/mips: Guard check_insn with INSN_R5900 check
  target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
  target/mips: Fix decoding mechanism of special R5900 opcodes
  target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
  target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
  linux-user: Update MIPS specific prctl() implementation

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2018-11-19 10:23:45 +00:00
parent d06491098b 90b27c4c3b
commit d1b3b1ee9d
4 changed files with 447 additions and 340 deletions
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9
MAINTAINERS
View file

@ -190,6 +190,7 @@ F: disas/microblaze.c
MIPS
M: Aurelien Jarno <aurelien@aurel32.net>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: target/mips/
F: hw/mips/
@ -336,6 +337,7 @@ F: target/arm/kvm.c
MIPS
M: James Hogan <jhogan@kernel.org>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: target/mips/kvm.c
@ -741,27 +743,32 @@ MIPS Machines
-------------
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/mips/mips_jazz.c
Malta
M: Aurelien Jarno <aurelien@aurel32.net>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/mips/mips_malta.c
Mipssim
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
R4000
M: Aurelien Jarno <aurelien@aurel32.net>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
@ -770,6 +777,7 @@ F: include/hw/isa/vt82c686.h
Boston
M: Paul Burton <pburton@wavecomp.com>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@ -1992,6 +2000,7 @@ F: disas/i386.c
MIPS target
M: Aurelien Jarno <aurelien@aurel32.net>
R: Stefan Markovic <smarkovic@wavecomp.com>
S: Maintained
F: tcg/mips/
F: disas/mips.c

18
linux-user/syscall.c
View file

@ -9554,9 +9554,25 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
{
CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
bool old_fr = env->CP0_Status & (1 << CP0St_FR);
bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
const unsigned int known_bits = TARGET_PR_FP_MODE_FR |
TARGET_PR_FP_MODE_FRE;
/* If nothing to change, return right away, successfully. */
if (old_fr == new_fr && old_fre == new_fre) {
return 0;
}
/* Check the value is valid */
if (arg2 & ~known_bits) {
return -TARGET_EOPNOTSUPP;
}
/* Setting FRE without FR is not supported. */
if (new_fre && !new_fr) {
return -TARGET_EOPNOTSUPP;
}
if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
/* FR1 is not supported */
return -TARGET_EOPNOTSUPP;
@ -9586,6 +9602,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
env->hflags |= MIPS_HFLAG_F64;
} else {
env->CP0_Status &= ~(1 << CP0St_FR);
env->hflags &= ~MIPS_HFLAG_F64;
}
if (new_fre) {
env->CP0_Config5 |= (1 << CP0C5_FRE);
@ -9594,6 +9611,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
}
} else {
env->CP0_Config5 &= ~(1 << CP0C5_FRE);
env->hflags &= ~MIPS_HFLAG_FRE;
}
return 0;

701
target/mips/translate.c
View file

@ -2138,10 +2138,10 @@ enum {
* MTSAH rs, immediate Move Halfword Count to Shift Amount Register
* PROT3W rd, rt Parallel Rotate 3 Words
*
* The TX79-specific Multimedia Instruction encodings
* ==================================================
* MMI (MultiMedia Instruction) encodings
* ======================================
*
* TX79 Multimedia Instruction encoding table keys:
* MMI instructions encoding table keys:
*
* * This code is reserved for future use. An attempt to execute it
* causes a Reserved Instruction exception.
@ -2152,7 +2152,7 @@ enum {
* DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
* to execute it causes a Reserved Instruction exception.
*
* TX79 Multimedia Instructions encoded by opcode field (MMI, LQ, SQ):
* MMI instructions encoded by opcode field (MMI, LQ, SQ):
*
* 31 26 0
* +--------+----------------------------------------+
@ -2174,13 +2174,13 @@ enum {
*/
enum {
TX79_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
TX79_LQ = 0x1E << 26, /* Same as OPC_MSA */
TX79_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
/*
* TX79 Multimedia Instructions with opcode field = MMI:
* MMI instructions with opcode field = MMI:
*
* 31 26 5 0
* +--------+-------------------------------+--------+
@ -2201,37 +2201,37 @@ enum {
* 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
*/
#define MASK_TX79_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
#define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
enum {
TX79_MMI_MADD = 0x00 | TX79_CLASS_MMI, /* Same as OPC_MADD */
TX79_MMI_MADDU = 0x01 | TX79_CLASS_MMI, /* Same as OPC_MADDU */
TX79_MMI_PLZCW = 0x04 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI0 = 0x08 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI2 = 0x09 | TX79_CLASS_MMI,
TX79_MMI_MFHI1 = 0x10 | TX79_CLASS_MMI, /* Same minor as OPC_MFHI */
TX79_MMI_MTHI1 = 0x11 | TX79_CLASS_MMI, /* Same minor as OPC_MTHI */
TX79_MMI_MFLO1 = 0x12 | TX79_CLASS_MMI, /* Same minor as OPC_MFLO */
TX79_MMI_MTLO1 = 0x13 | TX79_CLASS_MMI, /* Same minor as OPC_MTLO */
TX79_MMI_MULT1 = 0x18 | TX79_CLASS_MMI, /* Same minor as OPC_MULT */
TX79_MMI_MULTU1 = 0x19 | TX79_CLASS_MMI, /* Same minor as OPC_MULTU */
TX79_MMI_DIV1 = 0x1A | TX79_CLASS_MMI, /* Same minor as OPC_DIV */
TX79_MMI_DIVU1 = 0x1B | TX79_CLASS_MMI, /* Same minor as OPC_DIVU */
TX79_MMI_MADD1 = 0x20 | TX79_CLASS_MMI,
TX79_MMI_MADDU1 = 0x21 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI1 = 0x28 | TX79_CLASS_MMI,
TX79_MMI_CLASS_MMI3 = 0x29 | TX79_CLASS_MMI,
TX79_MMI_PMFHL = 0x30 | TX79_CLASS_MMI,
TX79_MMI_PMTHL = 0x31 | TX79_CLASS_MMI,
TX79_MMI_PSLLH = 0x34 | TX79_CLASS_MMI,
TX79_MMI_PSRLH = 0x36 | TX79_CLASS_MMI,
TX79_MMI_PSRAH = 0x37 | TX79_CLASS_MMI,
TX79_MMI_PSLLW = 0x3C | TX79_CLASS_MMI,
TX79_MMI_PSRLW = 0x3E | TX79_CLASS_MMI,
TX79_MMI_PSRAW = 0x3F | TX79_CLASS_MMI,
MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI,
MMI_OPC_MFHI1 = 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFHI */
MMI_OPC_MTHI1 = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */
MMI_OPC_MFLO1 = 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFLO */
MMI_OPC_MTLO1 = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */
MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */
MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI,
MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI1 = 0x28 | MMI_OPC_CLASS_MMI,
MMI_OPC_CLASS_MMI3 = 0x29 | MMI_OPC_CLASS_MMI,
MMI_OPC_PMFHL = 0x30 | MMI_OPC_CLASS_MMI,
MMI_OPC_PMTHL = 0x31 | MMI_OPC_CLASS_MMI,
MMI_OPC_PSLLH = 0x34 | MMI_OPC_CLASS_MMI,
MMI_OPC_PSRLH = 0x36 | MMI_OPC_CLASS_MMI,
MMI_OPC_PSRAH = 0x37 | MMI_OPC_CLASS_MMI,
MMI_OPC_PSLLW = 0x3C | MMI_OPC_CLASS_MMI,
MMI_OPC_PSRLW = 0x3E | MMI_OPC_CLASS_MMI,
MMI_OPC_PSRAW = 0x3F | MMI_OPC_CLASS_MMI,
};
/*
* TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI0:
* MMI instructions with opcode field = MMI and bits 5..0 = MMI0:
*
* 31 26 10 6 5 0
* +--------+----------------------+--------+--------+
@ -2252,37 +2252,37 @@ enum {
* 7 111 | * | * | PEXT5 | PPAC5
*/
#define MASK_TX79_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
#define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
enum {
TX79_MMI0_PADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PSUBW = (0x01 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PCGTW = (0x02 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PMAXW = (0x03 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PADDH = (0x04 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PSUBH = (0x05 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PCGTH = (0x06 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PMAXH = (0x07 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PADDB = (0x08 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PSUBB = (0x09 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PCGTB = (0x0A << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PADDSW = (0x10 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PSUBSW = (0x11 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PEXTLW = (0x12 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PPACW = (0x13 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PADDSH = (0x14 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PSUBSH = (0x15 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PEXTLH = (0x16 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PPACH = (0x17 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PADDSB = (0x18 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PSUBSB = (0x19 << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PEXTLB = (0x1A << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PPACB = (0x1B << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PEXT5 = (0x1E << 6) | TX79_MMI_CLASS_MMI0,
TX79_MMI0_PPAC5 = (0x1F << 6) | TX79_MMI_CLASS_MMI0,
MMI_OPC_0_PADDW = (0x00 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PSUBW = (0x01 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PCGTW = (0x02 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PMAXW = (0x03 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PADDH = (0x04 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PSUBH = (0x05 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PCGTH = (0x06 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PMAXH = (0x07 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PADDB = (0x08 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PSUBB = (0x09 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PCGTB = (0x0A << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PADDSW = (0x10 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PSUBSW = (0x11 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PEXTLW = (0x12 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PPACW = (0x13 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PADDSH = (0x14 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PSUBSH = (0x15 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PEXTLH = (0x16 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PPACH = (0x17 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PADDSB = (0x18 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PSUBSB = (0x19 << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PEXTLB = (0x1A << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PPACB = (0x1B << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PEXT5 = (0x1E << 6) | MMI_OPC_CLASS_MMI0,
MMI_OPC_0_PPAC5 = (0x1F << 6) | MMI_OPC_CLASS_MMI0,
};
/*
* TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI1:
* MMI instructions with opcode field = MMI and bits 5..0 = MMI1:
*
* 31 26 10 6 5 0
* +--------+----------------------+--------+--------+
@ -2303,30 +2303,30 @@ enum {
* 7 111 | * | * | * | *
*/
#define MASK_TX79_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
#define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
enum {
TX79_MMI1_PABSW = (0x01 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PCEQW = (0x02 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PMINW = (0x03 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PADSBH = (0x04 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PABSH = (0x05 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PCEQH = (0x06 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PMINH = (0x07 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PCEQB = (0x0A << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PADDUW = (0x10 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PSUBUW = (0x11 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PEXTUW = (0x12 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PADDUH = (0x14 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PSUBUH = (0x15 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PEXTUH = (0x16 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PADDUB = (0x18 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PSUBUB = (0x19 << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_PEXTUB = (0x1A << 6) | TX79_MMI_CLASS_MMI1,
TX79_MMI1_QFSRV = (0x1B << 6) | TX79_MMI_CLASS_MMI1,
MMI_OPC_1_PABSW = (0x01 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PCEQW = (0x02 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PMINW = (0x03 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PADSBH = (0x04 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PABSH = (0x05 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PCEQH = (0x06 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PMINH = (0x07 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PCEQB = (0x0A << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PADDUW = (0x10 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PSUBUW = (0x11 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PEXTUW = (0x12 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PADDUH = (0x14 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PSUBUH = (0x15 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PEXTUH = (0x16 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PADDUB = (0x18 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PSUBUB = (0x19 << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_PEXTUB = (0x1A << 6) | MMI_OPC_CLASS_MMI1,
MMI_OPC_1_QFSRV = (0x1B << 6) | MMI_OPC_CLASS_MMI1,
};
/*
* TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI2:
* MMI instructions with opcode field = MMI and bits 5..0 = MMI2:
*
* 31 26 10 6 5 0
* +--------+----------------------+--------+--------+
@ -2347,34 +2347,34 @@ enum {
* 7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
*/
#define MASK_TX79_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
#define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
enum {
TX79_MMI2_PMADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PSLLVW = (0x02 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PSRLVW = (0x03 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMSUBW = (0x04 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMFHI = (0x08 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMFLO = (0x09 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PINTH = (0x0A << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMULTW = (0x0C << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PDIVW = (0x0D << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PCPYLD = (0x0E << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMADDH = (0x10 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PHMADH = (0x11 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PAND = (0x12 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PXOR = (0x13 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMSUBH = (0x14 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PHMSBH = (0x15 << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PEXEH = (0x1A << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PREVH = (0x1B << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PMULTH = (0x1C << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PDIVBW = (0x1D << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PEXEW = (0x1E << 6) | TX79_MMI_CLASS_MMI2,
TX79_MMI2_PROT3W = (0x1F << 6) | TX79_MMI_CLASS_MMI2,
MMI_OPC_2_PMADDW = (0x00 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PSLLVW = (0x02 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PSRLVW = (0x03 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMSUBW = (0x04 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMFHI = (0x08 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMFLO = (0x09 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PINTH = (0x0A << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMULTW = (0x0C << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PDIVW = (0x0D << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PCPYLD = (0x0E << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMADDH = (0x10 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PHMADH = (0x11 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PAND = (0x12 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PXOR = (0x13 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMSUBH = (0x14 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PHMSBH = (0x15 << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PEXEH = (0x1A << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PREVH = (0x1B << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PMULTH = (0x1C << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PDIVBW = (0x1D << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PEXEW = (0x1E << 6) | MMI_OPC_CLASS_MMI2,
MMI_OPC_2_PROT3W = (0x1F << 6) | MMI_OPC_CLASS_MMI2,
};
/*
* TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI3:
* MMI instructions with opcode field = MMI and bits 5..0 = MMI3:
*
* 31 26 10 6 5 0
* +--------+----------------------+--------+--------+
@ -2395,21 +2395,21 @@ enum {
* 7 111 | * | * | PEXCW | *
*/
#define MASK_TX79_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
#define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
enum {
TX79_MMI3_PMADDUW = (0x00 << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PSRAVW = (0x03 << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PMTHI = (0x08 << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PMTLO = (0x09 << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PINTEH = (0x0A << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PMULTUW = (0x0C << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PDIVUW = (0x0D << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PCPYUD = (0x0E << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_POR = (0x12 << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PNOR = (0x13 << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PEXCH = (0x1A << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PCPYH = (0x1B << 6) | TX79_MMI_CLASS_MMI3,
TX79_MMI3_PEXCW = (0x1E << 6) | TX79_MMI_CLASS_MMI3,
MMI_OPC_3_PMADDUW = (0x00 << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PSRAVW = (0x03 << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PMTHI = (0x08 << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PMTLO = (0x09 << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PINTEH = (0x0A << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PMULTUW = (0x0C << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PDIVUW = (0x0D << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PCPYUD = (0x0E << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_POR = (0x12 << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PNOR = (0x13 << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PEXCH = (0x1A << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PCPYH = (0x1B << 6) | MMI_OPC_CLASS_MMI3,
MMI_OPC_3_PEXCW = (0x1E << 6) | MMI_OPC_CLASS_MMI3,
};
/* global register indices */
@ -4359,24 +4359,56 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) {
/* Treat as NOP. */
return;
}
switch (opc) {
case MMI_OPC_MFHI1:
tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
break;
case MMI_OPC_MFLO1:
tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]);
break;
case MMI_OPC_MTHI1:
if (reg != 0) {
tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
} else {
tcg_gen_movi_tl(cpu_HI[1], 0);
}
break;
case MMI_OPC_MTLO1:
if (reg != 0) {
tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
} else {
tcg_gen_movi_tl(cpu_LO[1], 0);
}
break;
default:
MIPS_INVAL("mfthilo1 TX79");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
{
if (reg == 0 && (opc == OPC_MFHI || opc == TX79_MMI_MFHI1 ||
opc == OPC_MFLO || opc == TX79_MMI_MFLO1)) {
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
return;
}
if (acc != 0) {
if (!(ctx->insn_flags & INSN_R5900)) {
check_dsp(ctx);
}
check_dsp(ctx);
}
switch (opc) {
case OPC_MFHI:
case TX79_MMI_MFHI1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
@ -4387,7 +4419,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MFLO:
case TX79_MMI_MFLO1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
@ -4398,7 +4429,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MTHI:
case TX79_MMI_MTHI1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@ -4413,7 +4443,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MTLO:
case TX79_MMI_MTLO1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@ -4714,6 +4743,63 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_temp_free(t1);
}
static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
{
TCGv t0, t1;
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
switch (opc) {
case MMI_OPC_DIV1:
{
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
tcg_gen_ext32s_tl(t0, t0);
tcg_gen_ext32s_tl(t1, t1);
tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
tcg_gen_movi_tl(t3, 0);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_div_tl(cpu_LO[1], t0, t1);
tcg_gen_rem_tl(cpu_HI[1], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
tcg_temp_free(t3);
tcg_temp_free(t2);
}
break;
case MMI_OPC_DIVU1:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
tcg_gen_divu_tl(cpu_LO[1], t0, t1);
tcg_gen_remu_tl(cpu_HI[1], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
tcg_temp_free(t3);
tcg_temp_free(t2);
}
break;
default:
MIPS_INVAL("div1 TX79");
generate_exception_end(ctx, EXCP_RI);
goto out;
}
out:
tcg_temp_free(t0);
tcg_temp_free(t1);
}
static void gen_muldiv(DisasContext *ctx, uint32_t opc,
int acc, int rs, int rt)
{
@ -4726,14 +4812,11 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
if (acc != 0) {
if (!(ctx->insn_flags & INSN_R5900)) {
check_dsp(ctx);
}
check_dsp(ctx);
}
switch (opc) {
case OPC_DIV:
case TX79_MMI_DIV1:
{
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
@ -4755,7 +4838,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
break;
case OPC_DIVU:
case TX79_MMI_DIVU1:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
@ -4939,7 +5021,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
switch (opc) {
case TX79_MMI_MULT1:
case MMI_OPC_MULT1:
acc = 1;
/* Fall through */
case OPC_MULT:
@ -4958,7 +5040,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free_i32(t3);
}
break;
case TX79_MMI_MULTU1:
case MMI_OPC_MULTU1:
acc = 1;
/* Fall through */
case OPC_MULTU:
@ -23781,6 +23863,53 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
{
int rs = extract32(ctx->opcode, 21, 5);
int rt = extract32(ctx->opcode, 16, 5);
int rd = extract32(ctx->opcode, 11, 5);
uint32_t op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
case OPC_MFLO:
gen_HILO(ctx, op1, 0, rd);
break;
case OPC_MTHI:
case OPC_MTLO: /* Move to HI/LO */
gen_HILO(ctx, op1, 0, rs);
break;
case OPC_MULT:
case OPC_MULTU:
gen_mul_txx9(ctx, op1, rd, rs, rt);
break;
case OPC_DIV:
case OPC_DIVU:
gen_muldiv(ctx, op1, 0, rs, rt);
break;
#if defined(TARGET_MIPS64)
case OPC_DMULT:
case OPC_DMULTU:
case OPC_DDIV:
case OPC_DDIVU:
check_insn_opc_user_only(ctx, INSN_R5900);
gen_muldiv(ctx, op1, 0, rs, rt);
break;
#endif
case OPC_JR:
gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
break;
default: /* Invalid */
MIPS_INVAL("special_tx79");
generate_exception_end(ctx, EXCP_RI);
break;
}
}
static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@ -23796,7 +23925,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
INSN_LOONGSON2E | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
@ -23823,8 +23952,6 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, INSN_VR54XX);
op1 = MASK_MUL_VR54XX(ctx->opcode);
gen_mul_vr54xx(ctx, op1, rd, rs, rt);
} else if (ctx->insn_flags & INSN_R5900) {
gen_mul_txx9(ctx, op1, rd, rs, rt);
} else {
gen_muldiv(ctx, op1, rd & 3, rs, rt);
}
@ -23839,7 +23966,6 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_DDIV:
case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3);
check_insn_opc_user_only(ctx, INSN_R5900);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
break;
@ -24066,6 +24192,8 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
default:
if (ctx->insn_flags & ISA_MIPS32R6) {
decode_opc_special_r6(env, ctx);
} else if (ctx->insn_flags & INSN_R5900) {
decode_opc_special_tx79(env, ctx);
} else {
decode_opc_special_legacy(env, ctx);
}
@ -26336,37 +26464,37 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI0(ctx->opcode);
uint32_t opc = MASK_MMI0(ctx->opcode);
switch (opc) {
case TX79_MMI0_PADDW: /* TODO: TX79_MMI0_PADDW */
case TX79_MMI0_PSUBW: /* TODO: TX79_MMI0_PSUBW */
case TX79_MMI0_PCGTW: /* TODO: TX79_MMI0_PCGTW */
case TX79_MMI0_PMAXW: /* TODO: TX79_MMI0_PMAXW */
case TX79_MMI0_PADDH: /* TODO: TX79_MMI0_PADDH */
case TX79_MMI0_PSUBH: /* TODO: TX79_MMI0_PSUBH */
case TX79_MMI0_PCGTH: /* TODO: TX79_MMI0_PCGTH */
case TX79_MMI0_PMAXH: /* TODO: TX79_MMI0_PMAXH */
case TX79_MMI0_PADDB: /* TODO: TX79_MMI0_PADDB */
case TX79_MMI0_PSUBB: /* TODO: TX79_MMI0_PSUBB */
case TX79_MMI0_PCGTB: /* TODO: TX79_MMI0_PCGTB */
case TX79_MMI0_PADDSW: /* TODO: TX79_MMI0_PADDSW */
case TX79_MMI0_PSUBSW: /* TODO: TX79_MMI0_PSUBSW */
case TX79_MMI0_PEXTLW: /* TODO: TX79_MMI0_PEXTLW */
case TX79_MMI0_PPACW: /* TODO: TX79_MMI0_PPACW */
case TX79_MMI0_PADDSH: /* TODO: TX79_MMI0_PADDSH */
case TX79_MMI0_PSUBSH: /* TODO: TX79_MMI0_PSUBSH */
case TX79_MMI0_PEXTLH: /* TODO: TX79_MMI0_PEXTLH */
case TX79_MMI0_PPACH: /* TODO: TX79_MMI0_PPACH */
case TX79_MMI0_PADDSB: /* TODO: TX79_MMI0_PADDSB */
case TX79_MMI0_PSUBSB: /* TODO: TX79_MMI0_PSUBSB */
case TX79_MMI0_PEXTLB: /* TODO: TX79_MMI0_PEXTLB */
case TX79_MMI0_PPACB: /* TODO: TX79_MMI0_PPACB */
case TX79_MMI0_PEXT5: /* TODO: TX79_MMI0_PEXT5 */
case TX79_MMI0_PPAC5: /* TODO: TX79_MMI0_PPAC5 */
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI0 */
case MMI_OPC_0_PADDW: /* TODO: MMI_OPC_0_PADDW */
case MMI_OPC_0_PSUBW: /* TODO: MMI_OPC_0_PSUBW */
case MMI_OPC_0_PCGTW: /* TODO: MMI_OPC_0_PCGTW */
case MMI_OPC_0_PMAXW: /* TODO: MMI_OPC_0_PMAXW */
case MMI_OPC_0_PADDH: /* TODO: MMI_OPC_0_PADDH */
case MMI_OPC_0_PSUBH: /* TODO: MMI_OPC_0_PSUBH */
case MMI_OPC_0_PCGTH: /* TODO: MMI_OPC_0_PCGTH */
case MMI_OPC_0_PMAXH: /* TODO: MMI_OPC_0_PMAXH */
case MMI_OPC_0_PADDB: /* TODO: MMI_OPC_0_PADDB */
case MMI_OPC_0_PSUBB: /* TODO: MMI_OPC_0_PSUBB */
case MMI_OPC_0_PCGTB: /* TODO: MMI_OPC_0_PCGTB */
case MMI_OPC_0_PADDSW: /* TODO: MMI_OPC_0_PADDSW */
case MMI_OPC_0_PSUBSW: /* TODO: MMI_OPC_0_PSUBSW */
case MMI_OPC_0_PEXTLW: /* TODO: MMI_OPC_0_PEXTLW */
case MMI_OPC_0_PPACW: /* TODO: MMI_OPC_0_PPACW */
case MMI_OPC_0_PADDSH: /* TODO: MMI_OPC_0_PADDSH */
case MMI_OPC_0_PSUBSH: /* TODO: MMI_OPC_0_PSUBSH */
case MMI_OPC_0_PEXTLH: /* TODO: MMI_OPC_0_PEXTLH */
case MMI_OPC_0_PPACH: /* TODO: MMI_OPC_0_PPACH */
case MMI_OPC_0_PADDSB: /* TODO: MMI_OPC_0_PADDSB */
case MMI_OPC_0_PSUBSB: /* TODO: MMI_OPC_0_PSUBSB */
case MMI_OPC_0_PEXTLB: /* TODO: MMI_OPC_0_PEXTLB */
case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */
case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */
case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI0");
@ -26375,30 +26503,30 @@ static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI1(ctx->opcode);
uint32_t opc = MASK_MMI1(ctx->opcode);
switch (opc) {
case TX79_MMI1_PABSW: /* TODO: TX79_MMI1_PABSW */
case TX79_MMI1_PCEQW: /* TODO: TX79_MMI1_PCEQW */
case TX79_MMI1_PMINW: /* TODO: TX79_MMI1_PMINW */
case TX79_MMI1_PADSBH: /* TODO: TX79_MMI1_PADSBH */
case TX79_MMI1_PABSH: /* TODO: TX79_MMI1_PABSH */
case TX79_MMI1_PCEQH: /* TODO: TX79_MMI1_PCEQH */
case TX79_MMI1_PMINH: /* TODO: TX79_MMI1_PMINH */
case TX79_MMI1_PCEQB: /* TODO: TX79_MMI1_PCEQB */
case TX79_MMI1_PADDUW: /* TODO: TX79_MMI1_PADDUW */
case TX79_MMI1_PSUBUW: /* TODO: TX79_MMI1_PSUBUW */
case TX79_MMI1_PEXTUW: /* TODO: TX79_MMI1_PEXTUW */
case TX79_MMI1_PADDUH: /* TODO: TX79_MMI1_PADDUH */
case TX79_MMI1_PSUBUH: /* TODO: TX79_MMI1_PSUBUH */
case TX79_MMI1_PEXTUH: /* TODO: TX79_MMI1_PEXTUH */
case TX79_MMI1_PADDUB: /* TODO: TX79_MMI1_PADDUB */
case TX79_MMI1_PSUBUB: /* TODO: TX79_MMI1_PSUBUB */
case TX79_MMI1_PEXTUB: /* TODO: TX79_MMI1_PEXTUB */
case TX79_MMI1_QFSRV: /* TODO: TX79_MMI1_QFSRV */
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI1 */
case MMI_OPC_1_PABSW: /* TODO: MMI_OPC_1_PABSW */
case MMI_OPC_1_PCEQW: /* TODO: MMI_OPC_1_PCEQW */
case MMI_OPC_1_PMINW: /* TODO: MMI_OPC_1_PMINW */
case MMI_OPC_1_PADSBH: /* TODO: MMI_OPC_1_PADSBH */
case MMI_OPC_1_PABSH: /* TODO: MMI_OPC_1_PABSH */
case MMI_OPC_1_PCEQH: /* TODO: MMI_OPC_1_PCEQH */
case MMI_OPC_1_PMINH: /* TODO: MMI_OPC_1_PMINH */
case MMI_OPC_1_PCEQB: /* TODO: MMI_OPC_1_PCEQB */
case MMI_OPC_1_PADDUW: /* TODO: MMI_OPC_1_PADDUW */
case MMI_OPC_1_PSUBUW: /* TODO: MMI_OPC_1_PSUBUW */
case MMI_OPC_1_PEXTUW: /* TODO: MMI_OPC_1_PEXTUW */
case MMI_OPC_1_PADDUH: /* TODO: MMI_OPC_1_PADDUH */
case MMI_OPC_1_PSUBUH: /* TODO: MMI_OPC_1_PSUBUH */
case MMI_OPC_1_PEXTUH: /* TODO: MMI_OPC_1_PEXTUH */
case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */
case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */
case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */
case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
@ -26407,34 +26535,34 @@ static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI2(ctx->opcode);
uint32_t opc = MASK_MMI2(ctx->opcode);
switch (opc) {
case TX79_MMI2_PMADDW: /* TODO: TX79_MMI2_PMADDW */
case TX79_MMI2_PSLLVW: /* TODO: TX79_MMI2_PSLLVW */
case TX79_MMI2_PSRLVW: /* TODO: TX79_MMI2_PSRLVW */
case TX79_MMI2_PMSUBW: /* TODO: TX79_MMI2_PMSUBW */
case TX79_MMI2_PMFHI: /* TODO: TX79_MMI2_PMFHI */
case TX79_MMI2_PMFLO: /* TODO: TX79_MMI2_PMFLO */
case TX79_MMI2_PINTH: /* TODO: TX79_MMI2_PINTH */
case TX79_MMI2_PMULTW: /* TODO: TX79_MMI2_PMULTW */
case TX79_MMI2_PDIVW: /* TODO: TX79_MMI2_PDIVW */
case TX79_MMI2_PCPYLD: /* TODO: TX79_MMI2_PCPYLD */
case TX79_MMI2_PMADDH: /* TODO: TX79_MMI2_PMADDH */
case TX79_MMI2_PHMADH: /* TODO: TX79_MMI2_PHMADH */
case TX79_MMI2_PAND: /* TODO: TX79_MMI2_PAND */
case TX79_MMI2_PXOR: /* TODO: TX79_MMI2_PXOR */
case TX79_MMI2_PMSUBH: /* TODO: TX79_MMI2_PMSUBH */
case TX79_MMI2_PHMSBH: /* TODO: TX79_MMI2_PHMSBH */
case TX79_MMI2_PEXEH: /* TODO: TX79_MMI2_PEXEH */
case TX79_MMI2_PREVH: /* TODO: TX79_MMI2_PREVH */
case TX79_MMI2_PMULTH: /* TODO: TX79_MMI2_PMULTH */
case TX79_MMI2_PDIVBW: /* TODO: TX79_MMI2_PDIVBW */
case TX79_MMI2_PEXEW: /* TODO: TX79_MMI2_PEXEW */
case TX79_MMI2_PROT3W: /* TODO: TX79_MMI2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI2 */
case MMI_OPC_2_PMADDW: /* TODO: MMI_OPC_2_PMADDW */
case MMI_OPC_2_PSLLVW: /* TODO: MMI_OPC_2_PSLLVW */
case MMI_OPC_2_PSRLVW: /* TODO: MMI_OPC_2_PSRLVW */
case MMI_OPC_2_PMSUBW: /* TODO: MMI_OPC_2_PMSUBW */
case MMI_OPC_2_PMFHI: /* TODO: MMI_OPC_2_PMFHI */
case MMI_OPC_2_PMFLO: /* TODO: MMI_OPC_2_PMFLO */
case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */
case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */
case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */
case MMI_OPC_2_PCPYLD: /* TODO: MMI_OPC_2_PCPYLD */
case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */
case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */
case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */
case MMI_OPC_2_PXOR: /* TODO: MMI_OPC_2_PXOR */
case MMI_OPC_2_PMSUBH: /* TODO: MMI_OPC_2_PMSUBH */
case MMI_OPC_2_PHMSBH: /* TODO: MMI_OPC_2_PHMSBH */
case MMI_OPC_2_PEXEH: /* TODO: MMI_OPC_2_PEXEH */
case MMI_OPC_2_PREVH: /* TODO: MMI_OPC_2_PREVH */
case MMI_OPC_2_PMULTH: /* TODO: MMI_OPC_2_PMULTH */
case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */
case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
@ -26443,25 +26571,25 @@ static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI3(ctx->opcode);
uint32_t opc = MASK_MMI3(ctx->opcode);
switch (opc) {
case TX79_MMI3_PMADDUW: /* TODO: TX79_MMI3_PMADDUW */
case TX79_MMI3_PSRAVW: /* TODO: TX79_MMI3_PSRAVW */
case TX79_MMI3_PMTHI: /* TODO: TX79_MMI3_PMTHI */
case TX79_MMI3_PMTLO: /* TODO: TX79_MMI3_PMTLO */
case TX79_MMI3_PINTEH: /* TODO: TX79_MMI3_PINTEH */
case TX79_MMI3_PMULTUW: /* TODO: TX79_MMI3_PMULTUW */
case TX79_MMI3_PDIVUW: /* TODO: TX79_MMI3_PDIVUW */
case TX79_MMI3_PCPYUD: /* TODO: TX79_MMI3_PCPYUD */
case TX79_MMI3_POR: /* TODO: TX79_MMI3_POR */
case TX79_MMI3_PNOR: /* TODO: TX79_MMI3_PNOR */
case TX79_MMI3_PEXCH: /* TODO: TX79_MMI3_PEXCH */
case TX79_MMI3_PCPYH: /* TODO: TX79_MMI3_PCPYH */
case TX79_MMI3_PEXCW: /* TODO: TX79_MMI3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI3 */
case MMI_OPC_3_PMADDUW: /* TODO: MMI_OPC_3_PMADDUW */
case MMI_OPC_3_PSRAVW: /* TODO: MMI_OPC_3_PSRAVW */
case MMI_OPC_3_PMTHI: /* TODO: MMI_OPC_3_PMTHI */
case MMI_OPC_3_PMTLO: /* TODO: MMI_OPC_3_PMTLO */
case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
@ -26470,56 +26598,56 @@ static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
uint32_t opc = MASK_MMI(ctx->opcode);
int rs = extract32(ctx->opcode, 21, 5);
int rt = extract32(ctx->opcode, 16, 5);
int rd = extract32(ctx->opcode, 11, 5);
switch (opc) {
case TX79_MMI_CLASS_MMI0:
decode_tx79_mmi0(env, ctx);
case MMI_OPC_CLASS_MMI0:
decode_mmi0(env, ctx);
break;
case TX79_MMI_CLASS_MMI1:
decode_tx79_mmi1(env, ctx);
case MMI_OPC_CLASS_MMI1:
decode_mmi1(env, ctx);
break;
case TX79_MMI_CLASS_MMI2:
decode_tx79_mmi2(env, ctx);
case MMI_OPC_CLASS_MMI2:
decode_mmi2(env, ctx);
break;
case TX79_MMI_CLASS_MMI3:
decode_tx79_mmi3(env, ctx);
case MMI_OPC_CLASS_MMI3:
decode_mmi3(env, ctx);
break;
case TX79_MMI_MULT1:
case TX79_MMI_MULTU1:
case MMI_OPC_MULT1:
case MMI_OPC_MULTU1:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
case TX79_MMI_DIV1:
case TX79_MMI_DIVU1:
gen_muldiv(ctx, opc, 1, rs, rt);
case MMI_OPC_DIV1:
case MMI_OPC_DIVU1:
gen_div1_tx79(ctx, opc, rs, rt);
break;
case TX79_MMI_MTLO1:
case TX79_MMI_MTHI1:
gen_HILO(ctx, opc, 1, rs);
case MMI_OPC_MTLO1:
case MMI_OPC_MTHI1:
gen_HILO1_tx79(ctx, opc, rs);
break;
case TX79_MMI_MFLO1:
case TX79_MMI_MFHI1:
gen_HILO(ctx, opc, 1, rd);
case MMI_OPC_MFLO1:
case MMI_OPC_MFHI1:
gen_HILO1_tx79(ctx, opc, rd);
break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
case TX79_MMI_PSLLH: /* TODO: TX79_MMI_PSLLH */
case TX79_MMI_PSRLH: /* TODO: TX79_MMI_PSRLH */
case TX79_MMI_PSRAH: /* TODO: TX79_MMI_PSRAH */
case TX79_MMI_PSLLW: /* TODO: TX79_MMI_PSLLW */
case TX79_MMI_PSRLW: /* TODO: TX79_MMI_PSRLW */
case TX79_MMI_PSRAW: /* TODO: TX79_MMI_PSRAW */
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_CLASS_MMI */
case MMI_OPC_MADD: /* TODO: MMI_OPC_MADD */
case MMI_OPC_MADDU: /* TODO: MMI_OPC_MADDU */
case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */
case MMI_OPC_MADD1: /* TODO: MMI_OPC_MADD1 */
case MMI_OPC_MADDU1: /* TODO: MMI_OPC_MADDU1 */
case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */
case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */
case MMI_OPC_PSLLH: /* TODO: MMI_OPC_PSLLH */
case MMI_OPC_PSRLH: /* TODO: MMI_OPC_PSRLH */
case MMI_OPC_PSRAH: /* TODO: MMI_OPC_PSRAH */
case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */
case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */
case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI */
break;
default:
MIPS_INVAL("TX79 MMI class");
@ -26528,14 +26656,14 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
}
}
static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_LQ */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_LQ */
}
static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */
}
/*
@ -26559,7 +26687,7 @@ static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
* In user mode, QEMU must verify the upper and lower 11 bits to distinguish
* between SQ and RDHWR, as the Linux kernel does.
*/
static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
{
int base = extract32(ctx->opcode, 21, 5);
int rt = extract32(ctx->opcode, 16, 5);
@ -26577,7 +26705,7 @@ static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
}
#endif
gen_tx79_sq(ctx, base, rt, offset);
gen_mmi_sq(ctx, base, rt, offset);
}
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
@ -27886,7 +28014,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SPECIAL2:
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_tx79_mmi(env, ctx);
decode_mmi(env, ctx);
} else if (ctx->insn_flags & ASE_MXU) {
decode_opc_mxu(env, ctx);
} else {
@ -27895,7 +28023,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SPECIAL3:
if (ctx->insn_flags & INSN_R5900) {
decode_tx79_sq(env, ctx); /* TX79_SQ */
decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
} else {
decode_opc_special3(env, ctx);
}
@ -28185,7 +28313,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_LL: /* Load and stores */
check_insn(ctx, ISA_MIPS2);
check_insn_opc_user_only(ctx, INSN_R5900);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
@ -28211,7 +28341,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn_opc_user_only(ctx, INSN_R5900);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
gen_st_cond(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
@ -28225,9 +28357,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_PREF:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
INSN_R5900);
/* Treat as NOP. */
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
/* Treat as NOP. */
}
break;
/* Floating point (COP1). */
@ -28479,7 +28614,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LLD:
check_insn_opc_user_only(ctx, INSN_R5900);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
/* fall through */
case OPC_LDL:
case OPC_LDR:
@ -28503,7 +28640,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_SCD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS3);
check_insn_opc_user_only(ctx, INSN_R5900);
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
gen_st_cond(ctx, op, rt, rs, imm);
break;
@ -28559,7 +28698,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MSA: /* OPC_MDMX */
if (ctx->insn_flags & INSN_R5900) {
decode_tx79_lq(env, ctx); /* TX79_LQ */
gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
} else {
/* MDMX: Not implemented. */
gen_msa(env, ctx);

59
target/mips/translate_init.inc.c
View file

@ -410,65 +410,6 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R5 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
/*
* The Toshiba TX System RISC TX79 Core Architecture manual
*
* https://wiki.qemu.org/File:C790.pdf
*
* describes the C790 processor that is a follow-up to the R5900.
* There are a few notable differences in that the R5900 FPU
*
* - is not IEEE 754-1985 compliant,
* - does not implement double format, and
* - its machine code is nonstandard.
*/
.name = "R5900",
.CP0_PRid = 0x00002E00,
/* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */
.CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),
.CP0_Status_rw_bitmask = 0xF4C79C1F,
#ifdef CONFIG_USER_ONLY
/*
* R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC
* emulation. For user only, QEMU is the kernel, so we emulate the traps
* by simply emulating the instructions directly.
*
* Note: Config1 is only used internally, the R5900 has only Config0.
*/
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
.CP0_LLAddr_shift = 4,
.CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),
.CP1_fcr31 = 0,
.CP1_fcr31_rw_bitmask = 0x0183FFFF,
#else
/*
* The R5900 COP1 FPU implements single-precision floating-point
* operations but is not entirely IEEE 754-1985 compatible. In
* particular,
*
* - NaN (not a number) and +/- infinities are not supported;
* - exception mechanisms are not fully supported;
* - denormalized numbers are not supported;
* - rounding towards nearest and +/- infinities are not supported;
* - computed results usually differs in the least significant bit;
* - saturations can differ more than the least significant bit.
*
* Since only rounding towards zero is supported, the two least
* significant bits of FCR31 are hardwired to 01.
*
* FPU emulation is disabled here until it is implemented.
*
* Note: Config1 is only used internally, the R5900 has only Config0.
*/
.CP0_Config1 = (47 << CP0C1_MMU),
#endif /* !CONFIG_USER_ONLY */
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_R5900 | ASE_MMI,
.mmu_type = MMU_TYPE_R4000,
},
{
/* A generic CPU supporting MIPS32 Release 6 ISA.
FIXME: Support IEEE 754-2008 FP.