From d2c33733c85c4df7cd0f5e0426a22e737d542516 Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Sun, 24 Jul 2011 17:47:18 +0300 Subject: [PATCH] pci_host: convert conf index and data ports to memory API Reviewed-by: Richard Henderson Signed-off-by: Avi Kivity --- hw/dec_pci.c | 13 ++++---- hw/grackle_pci.c | 13 ++++---- hw/pci_host.c | 86 +++++++++++++++++++++--------------------------- hw/pci_host.h | 16 ++++----- hw/piix_pci.c | 11 +++++-- hw/ppc4xx_pci.c | 10 +++--- hw/ppce500_pci.c | 21 ++++++------ hw/prep_pci.c | 10 ++++-- hw/unin_pci.c | 82 ++++++++++++++++++++++----------------------- 9 files changed, 130 insertions(+), 132 deletions(-) diff --git a/hw/dec_pci.c b/hw/dec_pci.c index a35f382052..1aec06611c 100644 --- a/hw/dec_pci.c +++ b/hw/dec_pci.c @@ -80,16 +80,15 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) static int pci_dec_21154_init_device(SysBusDevice *dev) { DECState *s; - int pci_mem_config, pci_mem_data; s = FROM_SYSBUS(DECState, dev); - pci_mem_config = pci_host_conf_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - pci_mem_data = pci_host_data_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, pci_mem_config); - sysbus_init_mmio(dev, 0x1000, pci_mem_data); + memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, + &s->host_state, "pci-conf-idx", 0x1000); + memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, + &s->host_state, "pci-data-idx", 0x1000); + sysbus_init_mmio_region(dev, &s->host_state.conf_mem); + sysbus_init_mmio_region(dev, &s->host_state.data_mem); return 0; } diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index 9a823e1c06..9d3ff7d555 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -92,16 +92,15 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, static int pci_grackle_init_device(SysBusDevice *dev) { GrackleState *s; - int pci_mem_config, pci_mem_data; s = FROM_SYSBUS(GrackleState, dev); - pci_mem_config = pci_host_conf_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - pci_mem_data = pci_host_data_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, pci_mem_config); - sysbus_init_mmio(dev, 0x1000, pci_mem_data); + memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, + &s->host_state, "pci-conf-idx", 0x1000); + memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, + &s->host_state, "pci-data-idx", 0x1000); + sysbus_init_mmio_region(dev, &s->host_state.conf_mem); + sysbus_init_mmio_region(dev, &s->host_state.data_mem); qemu_register_reset(pci_grackle_reset, &s->host_state); return 0; diff --git a/hw/pci_host.c b/hw/pci_host.c index 2e8a29f1e3..44c6c207a9 100644 --- a/hw/pci_host.c +++ b/hw/pci_host.c @@ -94,82 +94,72 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len) return val; } -static void pci_host_config_write(ReadWriteHandler *handler, - pcibus_t addr, uint32_t val, int len) +static void pci_host_config_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned len) { - PCIHostState *s = container_of(handler, PCIHostState, conf_handler); + PCIHostState *s = opaque; - PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n", + PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", __func__, addr, len, val); s->config_reg = val; } -static uint32_t pci_host_config_read(ReadWriteHandler *handler, - pcibus_t addr, int len) +static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr, + unsigned len) { - PCIHostState *s = container_of(handler, PCIHostState, conf_handler); + PCIHostState *s = opaque; uint32_t val = s->config_reg; - PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n", + PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", __func__, addr, len, val); return val; } -static void pci_host_data_write(ReadWriteHandler *handler, - pcibus_t addr, uint32_t val, int len) +static void pci_host_data_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned len) { - PCIHostState *s = container_of(handler, PCIHostState, data_handler); - PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", - addr, len, val); + PCIHostState *s = opaque; + PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n", + addr, len, (unsigned)val); if (s->config_reg & (1u << 31)) pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); } -static uint32_t pci_host_data_read(ReadWriteHandler *handler, - pcibus_t addr, int len) +static uint64_t pci_host_data_read(void *opaque, + target_phys_addr_t addr, unsigned len) { - PCIHostState *s = container_of(handler, PCIHostState, data_handler); + PCIHostState *s = opaque; uint32_t val; if (!(s->config_reg & (1 << 31))) return 0xffffffff; val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); - PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", + PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n", addr, len, val); return val; } -static void pci_host_init(PCIHostState *s) -{ - s->conf_handler.write = pci_host_config_write; - s->conf_handler.read = pci_host_config_read; - s->data_handler.write = pci_host_data_write; - s->data_handler.read = pci_host_data_read; -} +const MemoryRegionOps pci_host_conf_le_ops = { + .read = pci_host_config_read, + .write = pci_host_config_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; -int pci_host_conf_register_mmio(PCIHostState *s, int endian) -{ - pci_host_init(s); - return cpu_register_io_memory_simple(&s->conf_handler, endian); -} +const MemoryRegionOps pci_host_conf_be_ops = { + .read = pci_host_config_read, + .write = pci_host_config_write, + .endianness = DEVICE_BIG_ENDIAN, +}; -void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s) -{ - pci_host_init(s); - register_ioport_simple(&s->conf_handler, ioport, 4, 4); - sysbus_init_ioports(&s->busdev, ioport, 4); -} +const MemoryRegionOps pci_host_data_le_ops = { + .read = pci_host_data_read, + .write = pci_host_data_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +const MemoryRegionOps pci_host_data_be_ops = { + .read = pci_host_data_read, + .write = pci_host_data_write, + .endianness = DEVICE_BIG_ENDIAN, +}; -int pci_host_data_register_mmio(PCIHostState *s, int endian) -{ - pci_host_init(s); - return cpu_register_io_memory_simple(&s->data_handler, endian); -} -void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s) -{ - pci_host_init(s); - register_ioport_simple(&s->data_handler, ioport, 4, 1); - register_ioport_simple(&s->data_handler, ioport, 4, 2); - register_ioport_simple(&s->data_handler, ioport, 4, 4); - sysbus_init_ioports(&s->busdev, ioport, 4); -} diff --git a/hw/pci_host.h b/hw/pci_host.h index 7f551143bb..0211086d70 100644 --- a/hw/pci_host.h +++ b/hw/pci_host.h @@ -29,12 +29,11 @@ #define PCI_HOST_H #include "sysbus.h" -#include "rwhandler.h" struct PCIHostState { SysBusDevice busdev; - ReadWriteHandler conf_handler; - ReadWriteHandler data_handler; + MemoryRegion conf_mem; + MemoryRegion data_mem; MemoryRegion *address_space; uint32_t config_reg; PCIBus *bus; @@ -49,12 +48,9 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr, void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len); uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len); -/* for mmio */ -int pci_host_conf_register_mmio(PCIHostState *s, int endian); -int pci_host_data_register_mmio(PCIHostState *s, int endian); - -/* for ioio */ -void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s); -void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s); +extern const MemoryRegionOps pci_host_conf_le_ops; +extern const MemoryRegionOps pci_host_conf_be_ops; +extern const MemoryRegionOps pci_host_data_le_ops; +extern const MemoryRegionOps pci_host_data_be_ops; #endif /* PCI_HOST_H */ diff --git a/hw/piix_pci.c b/hw/piix_pci.c index c563c6e1a3..f892994eae 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -235,9 +235,16 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev) { I440FXState *s = FROM_SYSBUS(I440FXState, dev); - pci_host_conf_register_ioport(0xcf8, s); + memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, + "pci-conf-idx", 4); + sysbus_add_io(dev, 0xcf8, &s->conf_mem); + sysbus_init_ioports(&s->busdev, 0xcf8, 4); + + memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s, + "pci-conf-data", 4); + sysbus_add_io(dev, 0xcfc, &s->data_mem); + sysbus_init_ioports(&s->busdev, 0xcfc, 4); - pci_host_data_register_ioport(0xcfc, s); return 0; } diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index 52e2663a01..339b38ec7a 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -368,10 +368,12 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); /* CFGDATA */ - index = pci_host_data_register_mmio(&controller->pci_state, 1); - if (index < 0) - goto free; - cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index); + memory_region_init_io(&controller->pci_state.data_mem, + &pci_host_data_be_ops, + &controller->pci_state, "pci-conf-data", 4); + memory_region_add_subregion(get_system_memory(), + config_space + PCIC0_CFGDATA, + &controller->pci_state.data_mem); /* Internal registers */ index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 4390aeb559..2db365d0b6 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -79,8 +79,6 @@ struct PPCE500PCIState { uint32_t gasket_time; qemu_irq irq[4]; /* mmio maps */ - int cfgaddr; - int cfgdata; int reg; }; @@ -268,18 +266,18 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base) PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h); - cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, s->cfgaddr); - cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, s->cfgdata); + sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem); + sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem); cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, s->reg); } static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base) { - cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, - IO_MEM_UNASSIGNED); - cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, - IO_MEM_UNASSIGNED); + PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); + + sysbus_del_memory(dev, &h->conf_mem); + sysbus_del_memory(dev, &h->data_mem); cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE, IO_MEM_UNASSIGNED); } @@ -309,9 +307,10 @@ static int e500_pcihost_initfn(SysBusDevice *dev) pci_create_simple(b, 0, "e500-host-bridge"); - s->cfgaddr = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN); - s->cfgdata = pci_host_data_register_mmio(&s->pci_state, - DEVICE_LITTLE_ENDIAN); + memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, + "pci-conf-idx", 4); + memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, + "pci-conf-data", 4); s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s, DEVICE_BIG_ENDIAN); sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap); diff --git a/hw/prep_pci.c b/hw/prep_pci.c index c36232a808..55e4e25099 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -125,9 +125,15 @@ PCIBus *pci_prep_init(qemu_irq *pic, address_space_io, 0, 4); - pci_host_conf_register_ioport(0xcf8, s); + memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s, + "pci-conf-idx", 1); + memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem); + sysbus_init_ioports(&s->busdev, 0xcf8, 1); - pci_host_data_register_ioport(0xcfc, s); + memory_region_init_io(&s->conf_mem, &pci_host_data_be_ops, s, + "pci-conf-data", 1); + memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem); + sysbus_init_ioports(&s->busdev, 0xcfc, 1); PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read, PPC_PCIIO_write, s, diff --git a/hw/unin_pci.c b/hw/unin_pci.c index f896f8c76b..600cd1e5bd 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -41,7 +41,6 @@ static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; typedef struct UNINState { SysBusDevice busdev; PCIHostState host_state; - ReadWriteHandler data_handler; } UNINState; static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) @@ -100,67 +99,70 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) return retval; } -static void unin_data_write(ReadWriteHandler *handler, - pcibus_t addr, uint32_t val, int len) +static void unin_data_write(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned len) { - UNINState *s = container_of(handler, UNINState, data_handler); - UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val); + UNINState *s = opaque; + UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n", + addr, len, val); pci_data_write(s->host_state.bus, unin_get_config_reg(s->host_state.config_reg, addr), val, len); } -static uint32_t unin_data_read(ReadWriteHandler *handler, - pcibus_t addr, int len) +static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr, + unsigned len) { - UNINState *s = container_of(handler, UNINState, data_handler); + UNINState *s = opaque; uint32_t val; val = pci_data_read(s->host_state.bus, unin_get_config_reg(s->host_state.config_reg, addr), len); - UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val); + UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n", + addr, len, val); return val; } +static const MemoryRegionOps unin_data_ops = { + .read = unin_data_read, + .write = unin_data_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static int pci_unin_main_init_device(SysBusDevice *dev) { UNINState *s; - int pci_mem_config, pci_mem_data; /* Use values found on a real PowerMac */ /* Uninorth main bus */ s = FROM_SYSBUS(UNINState, dev); - pci_mem_config = pci_host_conf_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - s->data_handler.read = unin_data_read; - s->data_handler.write = unin_data_write; - pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, pci_mem_config); - sysbus_init_mmio(dev, 0x1000, pci_mem_data); + memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, + &s->host_state, "pci-conf-idx", 0x1000); + memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s, + "pci-conf-data", 0x1000); + sysbus_init_mmio_region(dev, &s->host_state.conf_mem); + sysbus_init_mmio_region(dev, &s->host_state.data_mem); qemu_register_reset(pci_unin_reset, &s->host_state); return 0; } + static int pci_u3_agp_init_device(SysBusDevice *dev) { UNINState *s; - int pci_mem_config, pci_mem_data; /* Uninorth U3 AGP bus */ s = FROM_SYSBUS(UNINState, dev); - pci_mem_config = pci_host_conf_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - s->data_handler.read = unin_data_read; - s->data_handler.write = unin_data_write; - pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, pci_mem_config); - sysbus_init_mmio(dev, 0x1000, pci_mem_data); + memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, + &s->host_state, "pci-conf-idx", 0x1000); + memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s, + "pci-conf-data", 0x1000); + sysbus_init_mmio_region(dev, &s->host_state.conf_mem); + sysbus_init_mmio_region(dev, &s->host_state.data_mem); qemu_register_reset(pci_unin_reset, &s->host_state); @@ -170,34 +172,32 @@ static int pci_u3_agp_init_device(SysBusDevice *dev) static int pci_unin_agp_init_device(SysBusDevice *dev) { UNINState *s; - int pci_mem_config, pci_mem_data; /* Uninorth AGP bus */ s = FROM_SYSBUS(UNINState, dev); - pci_mem_config = pci_host_conf_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - pci_mem_data = pci_host_data_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, pci_mem_config); - sysbus_init_mmio(dev, 0x1000, pci_mem_data); + memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, + &s->host_state, "pci-conf-idx", 0x1000); + memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, + &s->host_state, "pci-conf-data", 0x1000); + sysbus_init_mmio_region(dev, &s->host_state.conf_mem); + sysbus_init_mmio_region(dev, &s->host_state.data_mem); return 0; } static int pci_unin_internal_init_device(SysBusDevice *dev) { UNINState *s; - int pci_mem_config, pci_mem_data; /* Uninorth internal bus */ s = FROM_SYSBUS(UNINState, dev); - pci_mem_config = pci_host_conf_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - pci_mem_data = pci_host_data_register_mmio(&s->host_state, - DEVICE_LITTLE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, pci_mem_config); - sysbus_init_mmio(dev, 0x1000, pci_mem_data); + memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops, + &s->host_state, "pci-conf-idx", 0x1000); + memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops, + &s->host_state, "pci-conf-data", 0x1000); + sysbus_init_mmio_region(dev, &s->host_state.conf_mem); + sysbus_init_mmio_region(dev, &s->host_state.data_mem); return 0; }