target/i386: [tcg] Port to generic translation framework
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Emilio G. Cota <cota@braap.org> Tested-by: Emilio G. Cota <cota@braap.org> Message-Id: <150002267714.22386.5095442346868988808.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -8450,6 +8450,10 @@ static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,
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return max_insns;
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}
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static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu)
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{
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}
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static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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@ -8469,7 +8473,7 @@ static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
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/* The address covered by the breakpoint must be included in
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[tb->pc, tb->pc + tb->size) in order to for it to be
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properly cleared -- thus we increment the PC here so that
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the logic setting tb->size below does the right thing. */
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the generic logic setting tb->size later does the right thing. */
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dc->base.pc_next += 1;
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return true;
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} else {
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@ -8533,94 +8537,22 @@ static void i386_tr_disas_log(const DisasContextBase *dcbase,
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log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size, disas_flags);
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}
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static const TranslatorOps i386_tr_ops = {
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.init_disas_context = i386_tr_init_disas_context,
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.tb_start = i386_tr_tb_start,
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.insn_start = i386_tr_insn_start,
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.breakpoint_check = i386_tr_breakpoint_check,
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.translate_insn = i386_tr_translate_insn,
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.tb_stop = i386_tr_tb_stop,
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.disas_log = i386_tr_disas_log,
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};
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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{
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DisasContext dc1, *dc = &dc1;
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int num_insns;
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int max_insns;
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DisasContext dc;
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/* generate intermediate code */
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->base.tb = tb;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.pc_first = tb->pc;
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dc->base.pc_next = dc->base.pc_first;
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max_insns = tb->cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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}
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max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns);
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num_insns = 0;
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gen_tb_start(tb);
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for(;;) {
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i386_tr_insn_start(&dc->base, cs);
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num_insns++;
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if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
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CPUBreakpoint *bp;
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QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
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if (bp->pc == dc->base.pc_next) {
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if (i386_tr_breakpoint_check(&dc->base, cs, bp)) {
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break;
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}
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}
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}
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if (dc->base.is_jmp == DISAS_NORETURN) {
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break;
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}
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}
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if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
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gen_io_start();
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}
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i386_tr_translate_insn(&dc->base, cs);
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/* stop translation if indicated */
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if (dc->base.is_jmp) {
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break;
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}
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/* if single step mode, we generate only one instruction and
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generate an exception */
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if (dc->base.singlestep_enabled) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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break;
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}
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/* if too long translation, stop generation too */
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if (tcg_op_buf_full() ||
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num_insns >= max_insns) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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break;
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}
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if (singlestep) {
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dc->base.is_jmp = DISAS_TOO_MANY;
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break;
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}
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}
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i386_tr_tb_stop(&dc->base, cs);
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if (tb->cflags & CF_LAST_IO)
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gen_io_end();
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gen_tb_end(tb, num_insns);
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tb->size = dc->base.pc_next - dc->base.pc_first;
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tb->icount = num_insns;
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#ifdef DEBUG_DISAS
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(dc->base.pc_first)) {
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qemu_log_lock();
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qemu_log("----------------\n");
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i386_tr_disas_log(&dc->base, cs);
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qemu_log("\n");
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qemu_log_unlock();
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}
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#endif
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translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
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}
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void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
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